Abstract: Techniques to improve the immunity of wireless battery systems by transmitting heavily-coded signals, e.g., using multiple chips of a sequence for each bit of information, to trade data rate for interference or jamming immunity as a response once a noisy environment is identified. The techniques provide the system with a noise immunity operating mode (or high-immunity transmit and receive mode) that can improve resilience to interference or jamming by reducing the data rate. One option for reducing the data rate is by slowing down the transmission bit rate to reduce the occupied transmit bandwidth to minimize the probability of collisions with interfering signals. Another option is though digital coding methods using Forward Error Correction such as Convolutional Coding, Reed-Solomon Coding and Turbo coding. A third option is with RF spread spectrum techniques such as Direct Sequence Spread Spectrum (DSSS) or Frequency Hopped Spread Spectrum (FHSS).

Abstract: Techniques to improve the immunity of wireless battery systems by transmitting heavily-coded signals, e.g., using multiple chips of a sequence for each bit of information, to trade data rate for interference or jamming immunity as a response once a noisy environment is identified. The techniques provide the system with a noise immunity operating mode (or high-immunity transmit and receive mode) that can improve resilience to interference or jamming by reducing the data rate. One option for reducing the data rate is by slowing down the transmission bit rate to reduce the occupied transmit bandwidth to minimize the probability of collisions with interfering signals. Another option is though digital coding methods using Forward Error Correction such as Convolutional Coding, Reed-Solomon Coding and Turbo coding. A third option is with RF spread spectrum techniques such as Direct Sequence Spread Spectrum (DSSS) or Frequency Hopped Spread Spectrum (FHSS).

Abstract: A system for providing synchronous access to hardware resources includes a first network interface element to receive a network time signal from a data communication network and a memory to store sequence of one or more instructions selected from an instruction set of the first processing circuit. The sequence of one or more instructions include a first instruction that is configured to synchronize execution of a second instruction of the sequence of one or more instructions with the network time signal. The system further includes a first processing circuit to use the first instruction and a timing parameter associated with a second instruction to execute the second instruction in synchrony with the network time signal.

Abstract: Embodiments of the present disclosure provide systems and methods for maintaining timing precision in different operating modes of a device (e.g., a wireless node). A timing circuit may switch clock signals between two different modes (e.g., high power and low power) while preserving timing precision. In a high-power mode, the timing circuit may provide a high frequency clock signal, and in a lower-power mode, it may provide a low frequency clock signal. Moreover, the switching between the different clock signals may be synchronized to select edges of the low frequency clock signal.

Abstract: Embodiments of the present disclosure provide systems and methods for maintaining timing precision in different operating modes of a device (e.g., a wireless node). A timing circuit may switch clock signals between two different modes (e.g., high power and low power) while preserving timing precision. In a high-power mode, the timing circuit may provide a high frequency clock signal, and in a lower-power mode, it may provide a low frequency clock signal. Moreover, the switching between the different clock signals may be synchronized to select edges of the low frequency clock signal.

Abstract: A system for providing synchronous access to hardware resources includes a first network interface element to receive a network time signal from a data communication network and a memory to store sequence of one or more instructions selected from an instruction set of the first processing circuit. The sequence of one or more instructions include a first instruction that is configured to synchronize execution of a second instruction of the sequence of one or more instructions with the network time signal. The system further includes a first processing circuit to use the first instruction and a timing parameter associated with a second instruction to execute the second instruction in synchrony with the network time signal.