Abstract: One or more computing devices, systems, and/or methods for determining whether requests for content are fraudulent are provided. A request for content may be received from a first device. A first user profile associated with the first device may be identified. The first user profile may comprise activity information associated with the first device, demographic information associated with the first device and/or interest information associated with the first device. A user profile database may be analyzed to identify a set of user profiles similar to the first user profile. A relevance score associated with the request for content may be generated based upon the resource, the set of user profiles and/or the first user profile. The relevance score may be compared with a threshold relevance to determine whether the request for content is fraudulent.

Abstract: A method generates a delayed signal based on an input signal, and applies vector magnitude scaling to the delayed signal, generating one or more vector magnitude scaled signals. The input signal is added to the one or more vector magnitude scaled signals, generating one or more phase-shifted signals. Compensation scaling is applied to the one or more phase-shifted signals, generating one or more compensated signals. The input signal and the one or more compensated signals are combined, generating an interpolated output signal. The method may be implemented by a device or a system.

Abstract: A receiver circuit includes a feedback loop including a device. The receiver circuit also includes a register and a sequencer. The sequencer is configured to, responsive to an error signal being below a threshold value, cause the register to store a value indicative of the state of the feedback loop. The sequencer is also configured to cause the feedback loop to transition to a lower power state, and, responsive to a detected wake-up event, cause the previously stored value indicative of the state of the feedback loop to be loaded from the register into the device and enable the feedback loop.

Abstract: An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.

Abstract: A computer-implemented method for automatically generating a digitized menu, the computer-implemented method comprising: receiving an image associated with a non-digitized menu; performing an optical character recognition (OCR) operation on the received image, to identify characters and strings of characters comprising one or more words, to generate a text-readable document; determining whether the received image is skewed to generate a determination; for the determination providing an indication that the received image is skewed, performing skew detection and skew correction; clustering the identified characters and strings of characters to generate a clustered text-readable document; classifying the clusters, and associating the classified clusters to generate a classified, associated text-readable document; and for one or more items on the classified, associated text-readable document, obtaining an associated image; and providing the digitized menu comprising the associated image and the classified, associ

Abstract: A receiver circuit includes a feedback loop including a device. The receiver circuit also includes a register and a sequencer. The sequencer is configured to, responsive to an error signal being below a threshold value, cause the register to store a value indicative of the state of the feedback loop. The sequencer is also configured to cause the feedback loop to transition to a lower power state, and, responsive to a detected wake-up event, cause the previously stored value indicative of the state of the feedback loop to be loaded from the register into the device and enable the feedback loop.

Abstract: A receiver circuit includes an analog-to-digital converter (ADC), a decision feedback equalizer (DFE), a slicer, and a timing error detector (TED). The DFE is coupled to the ADC, and includes a first tap and a second tap. The slicer is coupled to the DFE. The TED is coupled to the slicer. The TED is configured to initialize timing of a sampling clock provided to the ADC while initializing the second tap of the DFE and holding the first tap of the DFE at a constant value.

Abstract: An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.

Abstract: A receiver circuit includes an ADC, a processing channel, and an interference detection path. The processing channel is configured to process data samples provided by the ADC, and includes a notch filter. The interference detection path is configured to detect interference in the data samples, and includes a slicer, a slicer error circuit, and an interference detection circuit. The slicer is configured to slice input of the notch filter. The slicer error circuit is configured to compute an error of the slicer. The interference detection circuit configured to detect an interference signal in the error of the slicer, and set the notch filter to attenuate the interference signal.

Abstract: This disclosure describes systems, methods, and devices related to the synchronization of image sensors with different exposure durations. In some embodiments, a system may include multiple image sensors, such as cameras, that have differing exposure durations. A data management component may be configured to receive sensor data from the image sensors. In addition, a synchronization component may be configured to transmit a shutter synchronization pulse to the image sensors. Finally, a tracking component may be configured to temporally center, based at least in part on the shutter synchronization pulse, the differing exposure durations of the image sensors. Various other systems and methods are also disclosed.

Abstract: A method includes receiving an input signal at a filter, where the filter includes a plurality of filter taps, and where each of a first filter tap and a second filter tap has a weighting coefficient. The method also includes shutting down the first filter tap based on the weighting coefficient of the first filter tap being below a threshold and the weighting coefficient of the second filter tap being below the threshold, where the second filter tap is next to the first filter tap.

Abstract: An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.

Abstract: A receiver circuit includes an analog-to-digital converter (ADC), a decision feedback equalizer (DFE), a slicer, and a timing error detector (TED). The DFE is coupled to the ADC, and includes a first tap and a second tap. The slicer is coupled to the DFE. The TED is coupled to the slicer. The TED is configured to initialize timing of a sampling clock provided to the ADC while initializing the second tap of the DFE and holding the first tap of the DFE at a constant value.

Abstract: A receiver circuit includes an ADC, a processing channel, and an interference detection path. The processing channel is configured to process data samples provided by the ADC, and includes a notch filter. The interference detection path is configured to detect interference in the data samples, and includes a slicer, a slicer error circuit, and an interference detection circuit. The slicer is configured to slice input of the notch filter. The slicer error circuit is configured to compute an error of the slicer. The interference detection circuit configured to detect an interference signal in the error of the slicer, and set the notch filter to attenuate the interference signal.

Abstract: A method includes receiving an input signal at a filter, where the filter includes a plurality of filter taps, and where each of a first filter tap and a second filter tap has a weighting coefficient. The method also includes shutting down the first filter tap based on the weighting coefficient of the first filter tap being below a threshold and the weighting coefficient of the second filter tap being below the threshold, where the second filter tap is next to the first filter tap.

Abstract: A receiver circuit includes a feedback loop including a device. The receiver circuit also includes a register and a sequencer. The sequencer is configured to, responsive to an error signal being below a threshold value, cause the register to store a value indicative of the state of the feedback loop. The sequencer is also configured to cause the feedback loop to transition to a lower power state, and, responsive to a detected wake-up event, cause the previously stored value indicative of the state of the feedback loop to be loaded from the register into the device and enable the feedback loop.

Abstract: This disclosure describes systems, methods, and devices related to the synchronization of image sensors with different exposure durations. In some embodiments, a system may include multiple image sensors, such as cameras, that have differing exposure durations. A data management component may be configured to receive sensor data from the image sensors. In addition, a synchronization component may be configured to transmit a shutter synchronization pulse to the image sensors. Finally, a tracking component may be configured to temporally center, based at least in part on the shutter synchronization pulse, the differing exposure durations of the image sensors. Various other systems and methods are also disclosed.

Abstract: This disclosure describes systems, methods, and devices related to the synchronization of image sensors with different exposure durations. In some embodiments, a system may include multiple image sensors, such as cameras, that have differing exposure durations. A data management component may be configured to receive sensor data from the image sensors. In addition, a synchronization component may be configured to transmit a shutter synchronization pulse to the image sensors. Finally, a tracking component may be configured to temporally center, based at least in part on the shutter synchronization pulse, the differing exposure durations of the image sensors. Various other systems and methods are also disclosed.

Abstract: Described herein are system(s), method(s), and apparatus for embedding personal video recorder functions at the picture level. In one embodiment, there is presented a computer readable medium for storing a data structure. The data structure comprises a picture header and at least one command following the picture header.

Abstract: Described herein are system(s), method(s), and apparatus for embedding personal video recorder functions at the picture level. In one embodiment, there is presented a computer readable medium for storing a data structure. The data structure comprises a picture header and at least one command following the picture header.