Abstract: Systems and techniques are provided for caching misaligned pixel tiles. A method includes determining a first codec region including a first region of a frame; determining whether pixels of a first version of a pixel tile were stored in a cache while coding blocks from a second codec region, the pixel tile corresponding to a location within the frame; based on whether the pixels were stored in the cache, determining whether to read the first version of the pixel tile from the cache or retrieve a second version of the pixel tile from a memory device, the second version of the pixel tile including pixels from the first codec region that are not in the first version of the pixel tile; and coding a block based on the first version of the pixel tile read from the cache or second version of the pixel tile retrieved from the memory device.

Abstract: Techniques are disclosed relating to performing remote cache invalidations. In some embodiments, primary processor circuitry is configured to, based on execution of a remote invalidate instruction (e.g., an ISA-defined instruction), send a cache invalidate command to coprocessor circuitry. The coprocessor circuitry includes coprocessor cache circuitry and cache invalidation control circuitry configured to, in response to the cache invalidate command sent by the primary processor, invalidate one or more cache lines in the coprocessor cache circuitry without executing any instructions on the coprocessor circuitry.

Abstract: Methods, systems, and apparatus include computer programs encoded on a computer-readable storage medium, including a method for providing content. Search results responsive to a query are identified including a first search result in a top set of search results, the first search result associated with a first entity. A first eligible content item is identified for presentation along with the search results, the first eligible content item associated with the first entity. A combined content item is identified that is a combination of the first search result and first eligible content item and is to be presented as a search result responsive to the query. The combined content item is augmented including: identifying entities related to the first entity, identifying content items that are associated with the related entities, selecting at least one identified content item, and using content from the selected content items to augment the combined content item.

Abstract: A system for interaction pattern recognition receives an input primary interaction and accesses clusters indicating interaction group patterns. Each cluster includes a respective primary interaction and secondary interactions linked to that primary interaction. Each cluster is identified by a respective non-fungible token.

Abstract: Some embodiments provide a novel method for dynamically deploying gateways for a first network connecting machines. The first network includes segments, routers, and a first gateway that connects to an external network. The method identifies a set of two or more segments that consumes more than a threshold amount of bandwidth of the first gateway. The identified set includes at least first and second segments. The method identifies one or more segment groups by aggregating two or more segments in the identified set. A first segment group includes the first and second segments and a third segment that is not in the identified set of two or more segments. The method configures a second gateway to process flows associated with each identified group including the first group. The method configures a set of routers to forward flows from machines of each segment of each identified group to the second gateway.

Abstract: A trained model and/or an edge client running on an edge device may obtain data from a data source (e.g., a security video camera) and determine, based on a result of processing the data using the model, whether to send an indication of an upcoming data/video stream to the provider network (e.g., indicating a bearer modification). The received indication may be used by the provider network to send a request to a serving wireless infrastructure (e.g., telco operator/wireless mobile core) for configuration of one or more resources on behalf of the edge device to process the upcoming data stream. The received indication may be used by the provider network in order to configure one or more resources at the provider network to process the upcoming data stream. The edge device initiates transmission of the data stream from the data source to the provider network via the serving wireless infrastructure.

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

Abstract: Example implementations relate to a method of dynamically updating a transport task of a UAV. The method includes receiving, at a transport-provider computing system, an item provider request for transportation of a plurality of packages from a loading location at a given future time. The method also includes assigning, by the transport-provider computing system, a respective transport task to each of a plurality of UAVs, where the respective transport task comprises an instruction to deploy to the loading location to pick up one or more of the plurality of packages. Further, the method includes identifying, by the transport-provider system, a first package while or after a first UAV picks up the first package. Yet further, the method includes based on the identifying of the first package, providing, by the transport-provider system, a task update to the first UAV to update the respective transport task of the first UAV.

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

Abstract: Example implementations relate to a method of dynamically updating a transport task of a UAV. The method includes receiving, at a transport-provider computing system, an item provider request for transportation of a plurality of packages from a loading location at a given future time. The method also includes assigning, by the transport-provider computing system, a respective transport task to each of a plurality of UAVs, where the respective transport task comprises an instruction to deploy to the loading location to pick up one or more of the plurality of packages. Further, the method includes identifying, by the transport-provider system, a first package while or after a first UAV picks up the first package. Yet further, the method includes based on the identifying of the first package, providing, by the transport-provider system, a task update to the first UAV to update the respective transport task of the first UAV.

Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include one or more queues and a transaction pipeline. The I/O agent circuit may issue, to the transaction pipeline from a queue of the one or more queues, a transaction of a series of transactions enqueued in a particular order. The I/O agent circuit may generate, at the transaction pipeline, a determination to return the transaction to the queue based on a detection of one or more conditions being satisfied. Based on the determination, the I/O agent circuit may reject, at the transaction pipeline, up to a threshold number of transactions that issued from the queue after the transaction issued. The I/O agent circuit may insert the transaction at a head of the queue such that the transaction is enqueued at the queue sequentially first for the series of transactions according to the particular order.

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.

Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

Abstract: An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.

Abstract: Example implementations relate to a method of dynamically updating a transport task of a UAV. The method includes receiving, at a transport-provider computing system, an item provider request for transportation of a plurality of packages from a loading location at a given future time. The method also includes assigning, by the transport-provider computing system, a respective transport task to each of a plurality of UAVs, where the respective transport task comprises an instruction to deploy to the loading location to pick up one or more of the plurality of packages. Further, the method includes identifying, by the transport-provider system, a first package while or after a first UAV picks up the first package. Yet further, the method includes based on the identifying of the first package, providing, by the transport-provider system, a task update to the first UAV to update the respective transport task of the first UAV.

Abstract: Embodiments herein disclose a method for optimizing power consumption in an electronic device comprising a plurality of RATs. The method includes determining a system bandwidth of the plurality of RATs available in the electronic device and mapping at least one portion of the system bandwidth to at least one power consumption level of a set of power consumption levels of the electronic device. Further, the method includes distributing the at least one portion of the system bandwidth across the plurality of RATs based on the at least one mapped power consumption level of the set of power consumption levels of the electronic device. Further, the method includes enforcing the distributed system bandwidth across the plurality of RATs in the electronic device and enabling at least one application to use the distributed system bandwidth across the plurality of RATs in the electronic device.