Abstract: An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower-order counter sub-module. The control logic includes a clock-gating integrated cell arranged to clock gate at least one higher-order counter sub-module dependent on a logical combination of outputs of the lower-order counter sub-module and to provide a multi-cycle path for resolution of a logical combination of outputs of any subsequent cascaded counter sub-modules. The control logic does not include any intervening memory device between the lower-order counter sub-module and the clock-gating integrated cell for use in determining a later control logic output.

Abstract: Methods and apparatuses are presented for piecewise aggregation of overhead messages. According to a method that is presented, that the method can include starting a timer having a time period during which a first radio access technology (RAT) of the UE attempts to obtain overhead messages from a cell. The method can also include obtaining, at a radio resource of the UE and during the time period, a first portion of the overhead messages from the cell. In addition, the method may include determining that the timer has expired and handing over the radio resource to a second RAT of the UE when the timer has expired. The method also may include aggregating the first portion of the overhead messages with a second portion of the overhead messages. Other aspects, embodiments, and features are also claimed and described.

Abstract: A single power supply level shifter has first and second inverters in tandem that invert an input signal from a first voltage domain and provide a first inverted signal and an output signal in a second voltage domain. A charging control circuit charges a capacitor towards the second voltage when the input signal is high, and conducts a discharge current from the capacitor during a transition of the input signal from high to low to accelerate a corresponding transition of the first inverted signal from low to high. A third inverter controls a current reduction transistor in series with the first inverter, and a third control transistor connected between the input and the charging control circuit to accelerate the flow of discharge current during the transition of the input signal from high to low.

Abstract: Flip-flop cells that enable time borrowing during the design of the IC to improve setup times while avoiding introducing meta-stability, and alternatively to avoid hold time violations. The flip-flop cells are connected with logic cells in functional data paths. The flip-flop cell has a clock signal controlling both its input and output. A selective delay cell selectively delays either a data signal input to the flip-flop cell or the clock signal controlling the flip-flop cell. The selectively delayed signal adjusts the timing (setup, hold and clock-to-output) of the data path.

Abstract: A signal delay cell for use in resolving hold time violations in an IC has a first multiplexer having a first functional data input node and a scan data input node TI and a second multiplexer having a second functional data input node, a second input node connected to the output of the first multiplexer and a flip-flop module. The propagation of a data input signal applied to the first multiplexer is delayed, and the hold margin of the flip-flop module is increased by transit through the first multiplexer. The signal delay cell is available to replace a flip-flop having a scan data hold problem, and also for use in solving a functional data violation in the same or another cell.

Abstract: An integrated circuit having reduced power consumption includes a clock-gating cell, a transistor and a flip-flop. The clock-gating cell receives a dynamic enable signal, generates a latched-enable signal and gates a clock signal provided to the flip-flop. The flip-flop includes first and second latches. The transistor receives an inverted latched-enable signal from the clock-gating cell and switches ON or OFF based on the logic state of the inverted latched-enable signal. The transistor provides a voltage signal to the flip-flop circuit based on the state of the flip-flop in order to control the state of the flip-flop, which reduces power consumption of the integrated circuit.

Abstract: A signal delay cell for use in resolving hold time violations in an IC has a first multiplexer having a first functional data input node and a scan data input node TI and a second multiplexer having a second functional data input node, a second input node connected to the output of the first multiplexer and a flip-flop module. The propagation of a data input signal applied to the first multiplexer is delayed, and the hold margin of the flip-flop module is increased by transit through the first multiplexer. The signal delay cell is available to replace a flip-flop having a scan data hold problem, and also for use in solving a functional data violation in the same or another cell.

Abstract: A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state.

Abstract: A single power supply level shifter has first and second inverters in tandem that invert an input signal from a first voltage domain and provide a first inverted signal and an output signal in a second voltage domain. A charging control circuit charges a capacitor towards the second voltage when the input signal is high, and conducts a discharge current from the capacitor during a transition of the input signal from high to low to accelerate a corresponding transition of the first inverted signal from low to high. A third inverter controls a current reduction transistor in series with the first inverter, and a third control transistor connected between the input and the charging control circuit to accelerate the flow of discharge current during the transition of the input signal from high to low.

Abstract: A scan flip-flop for generating an output signal based on a first input signal, a clock signal, a test input signal, a Launch On Shift (LOS) signal, a test enable signal, and a reset signal includes a logic circuit, a multiplexer and a flip-flop circuit. The logic circuit receives an inverted clock signal, the test enable signal, a intermediate test enable signal, and the LOS signal, and generates an intermediate output signal that is an inherent LOS scan enable signal. The multiplexer receives the test input signal and the intermediate output signal, and outputs the test input signal. The flip-flop circuit receives the test input signal as a second input signal, the clock signal, and the reset signal, and generates the output signal.

Abstract: Methods and apparatuses are presented for piecewise aggregation of overhead messages. According to a method that is presented, that the method can include starting a timer having a time period during which a first radio access technology (RAT) of the UE attempts to obtain overhead messages from a cell. . The method can also include obtaining, at a radio resource of the UE and during the time period, a first portion of the overhead messages from the cell. In addition, the method may include determining that the timer has expired and handing over the radio resource to a second RAT of the UE when the timer has expired. The method also may include aggregating the first portion of the overhead messages with a second portion of the overhead messages. Other aspects, embodiments, and features are also claimed and described.

Abstract: A scan flip-flop for generating an output signal based on a first input signal, a clock signal, a test input signal, a Launch On Shift (LOS) signal, a test enable signal, and a reset signal includes a logic circuit, a multiplexer and a flip-flop circuit. The logic circuit receives an inverted clock signal, the test enable signal, a intermediate test enable signal, and the LOS signal, and generates an intermediate output signal that is an inherent LOS scan enable signal. The multiplexer receives the test input signal and the intermediate output signal, and outputs the test input signal. The flip-flop circuit receives the test input signal as a second input signal, the clock signal, and the reset signal, and generates the output signal.

Abstract: Spare gate cells for inclusion in an integrated circuit have multiple inputs and outputs and are capable of selectively performing, concurrently, multiple logic functions on signals appearing at the inputs. Selection of required logic functions depends on the connections of at least one of the inputs of the spare cell. One of the outputs is fed back to an input of the spare gate cell to provide certain functionality while other outputs are set to a fixed logical value. The spare gate cell may be configured to perform NOR, OR and inverter operations on inputs simultaneously.

Abstract: Spare gate cells for inclusion in an integrated circuit have multiple inputs and outputs and are capable of selectively performing, concurrently, multiple logic functions on signals appearing at the inputs. Selection of required logic functions depends on the connections of at least one of the inputs of the spare cell. One of the outputs is fed back to an input of the spare gate cell to provide certain functionality while other outputs are set to a fixed logical value. The spare gate cell may be configured to perform NOR, OR and inverter operations on inputs simultaneously.

Abstract: A scan flip-flop includes a multiplexer, a flip-flop, and a logic circuit. The flip-flop includes a transmission gate that has two sets of clock-controlled transistors. The combined width of the clock-controlled transistors in a set equals the width of the single transistor commonly used in known scan flip-flop circuits. The logic circuit inhibits the clock signal from reaching one transistor of each set during scan mode, which reduces power consumption without sacrificing speed of operation.

Abstract: An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower order counter sub-module. The control logic is arranged to clock gate at least one higher order counter sub-module dependent on a logical combination of outputs of the lower order counter sub-module and where the control logic uses pipelining to store at least one previous control logic output for use in determining a later control logic output.

Abstract: A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state.

Abstract: An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower order counter sub-module. The control logic is arranged to clock gate at least one higher order counter sub-module dependent on a logical combination of outputs of the lower order counter sub-module and where the control logic uses pipelining to store at least one previous control logic output for use in determining a later control logic output.

Abstract: A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state.

Abstract: The present invention generally relates to estimating a customer's lifetime value to a company. The customer's lifetime value to the company can be based on remaining value of existing products and one or both of new purchase value and historic profitability. The remaining value and new purchase value for the customer may be estimated based on the customer's current customer segment and the customer's predicted future migration to a different customer segment. In addition, the remaining value may be estimated based on expected customer attrition, and the new purchase value may be estimated based on expected individual customer purchases.