Patents by Inventor Gaurav H. Agarwal

Gaurav H. Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of testing memory array at operational speed using scan
    Patent number: 7779316
    Abstract: A method and system for testing a chip at functional (operational) speed. The chip may include an integrated circuit having a number flops and memory arrays arranged into logically functioning elements. Additional flops may be included to output to one or more of the other flops in order to provide inputs to the flops at the functional speed such that the receiving flops executing at the functional speed according to the received input at a next functional clock pulse to facilitate testing the chip at the functional speed.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: August 17, 2010
    Assignee: Oracle America, Inc.
    Inventors: Ishwardutt Parulkar, Gaurav H. Agarwal, Krishna B. Rajan, Paul J. Dickinson
  • METHOD OF TESTING MEMORY ARRAY AT OPERATIONAL SPEED USING SCAN
    Publication number: 20090150729
    Abstract: A method and system for testing a chip at functional (operational) speed. The chip may include an integrated circuit having a number flops and memory arrays arranged into logically functioning elements. Additional flops may be included to output to one or more of the other flops in order to provide inputs to the flops at the functional speed such that the receiving flops executing at the functional speed according to the received input at a next functional clock pulse to facilitate testing the chip at the functional speed.
    Type: Application
    Filed: December 5, 2007
    Publication date: June 11, 2009
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Ishwardutt Parulkar, Gaurav H. Agarwal, Krishna B. Rajan, Paul J. Dickinson