Patents by Inventor Gaurav Khanna

Gaurav Khanna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140337824
    Abstract: An enhanced binder provides flexibility and certainty when selecting a version of a software library to load, and an enhanced loader prevents a library version vulnerable to a security flaw from being loaded. The binder can perform unification, implicit override, and/or redirection. Implicit override searches assembly-specific locations for an implicit_version, and override the previously chosen unification or other version with the implicit_version when the implicit_version is greater. The implicit_version gets updated with the individual assembly, whereas the unification_version gets updated with the framework. Redirection may override the implicit_version. Unlike redirection, an implicit_version does not recite an explicit range and is found outside application configuration files. The implicit_version is specified implicitly by the assembly without an XML declaration.
    Type: Application
    Filed: May 8, 2013
    Publication date: November 13, 2014
    Applicant: Microsoft Corporation
    Inventors: Eric St. John, Mohammad Rahim Bhojani, Alok Shriram, David Kean, Divya Swarnkar, Kumar Gaurav Khanna, Gaye Oncul Kok, Jan Kotas, Michael J. Rayhelson, Michael Rousos, Weitao Su, Matthew Charles Cohn, Zhanliang Chen
  • Publication number: 20140281457
    Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
    Type: Application
    Filed: March 29, 2013
    Publication date: September 18, 2014
    Inventors: Elierzer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt, Stephen A. Fischer, Bret L. Toll, Inder M. Sodhi, Alon Naveh, Ganapati N. Srinivasa, Ashish V. Choubal, Scott D. Hahn, David A. Koufaty, Russel J. Fenger, Gaurav Khanna, Eugene Gorbatov, Mishali Naik, Andrew J. Herdrich, Abirami Prabhakaran, Sanjeev S. Sahagirdar, Paul Brett, Paolo Narvaez, Andrew D. Henroid, Dheeraj R. Subbareddy
  • Patent number: 8782607
    Abstract: An error handling system is described herein that provides a facility for controlling the behavior of software when the software violates a contract condition. The system provides configurable runtime behavior that takes place when a contract fails. The error handling system provides an event that a hosting application or other software code can register to handle and that the system invokes upon detecting a contract failure. The application's response to the event determines how the system handles the failure. If the event is unhandled, the system triggers an escalation policy that allows an administrator or application to specify how the system handles contract failures. Thus, the error handling system provides increased control over the handling of contract failures within software code.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: July 15, 2014
    Assignee: Microsoft Corporation
    Inventors: Melitta L. G. Andersen, Michael Barnett, Manuel A. Fahndrich, Brian M. Grunkemeyer, Katherine E. King, Michael M. Magruder, Andrew J. Pardoe, Kumar Gaurav Khanna
  • Publication number: 20140189704
    Abstract: A heterogeneous processor architecture is described.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Paolo Narvaez, Ganapati N. Srinivasa, Eugene Gorbatov, Dheeraj R. Subbareddy, Mishali Naik, Alon Naveh, Abirami Prabhakaran, Eliezer Weissmann, David A. Koufaty, Paul Brett, Scott D. Hahn, Andrew J. Herdrich, Ravishankar Iyer, Nagabhushan Chitlur, Inder M. Sodhi, Gaurav Khanna, Russell J. Fenger
  • Publication number: 20140189285
    Abstract: A method is described that includes recognizing that TLB information of one or more hardware threads is to be invalidated. The method also includes determining which ones of the one or more hardware threads are in a state in which TLB information is flushed. The method also includes directing a TLB shootdown to those of the or more hardware threads that are in a state in which TLB information is not flushed.
    Type: Application
    Filed: December 29, 2012
    Publication date: July 3, 2014
    Inventors: Shaun M. CONRAD, Russell J. FENGER, Gaurav KHANNA, Rahul SETH, James B. CROSSLAND, Anil AGGARWAL
  • Publication number: 20140189297
    Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Paolo Narvaez, Ganapati N. Srinivasa, Eugene Gorbatov, Dheeraj R. Subbareddy, Mishali Naik, Alon Naveh, Abirami Prabhakaran, Eliezer Weissmann, David A. Koufaty, Paul Brett, Scott D. Hahn, Andrew J. Herdrich, Gaurav Khanna, Russell J. Fenger, Bryant E. Bigbee, Andrew D. Henroid
  • Publication number: 20140189302
    Abstract: A processor includes multiple physical cores that support multiple logical cores of different core types, where the core types include a big core type and a small core type. A multi-threaded application includes multiple software threads are concurrently executed by a first subset of logical cores in a first time slot. Based on data gathered from monitoring the execution in the first time slot, the processor selects a second subset of logical cores for concurrent execution of the software threads in a second time slot. Each logical core in the second subset has one of the core types that matches the characteristics of one of the software threads.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Dheeraj R. Subbareddy, Ganapati N. Srinivasa, David A. Koufaty, Scott D. Hahn, Mishali Naik, Paolo Narvaez, Abirami Prabhakaran, Eugene Gorbatov, Alon Naveh, Inder M. Sodhi, Eliezer Weissmann, Paul Brett, Gaurav Khanna, Russell J. Fenger
  • Publication number: 20140189299
    Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Paolo Narvaez, Ganapati N. Srinivasa, Eugene Gorbatov, Dheeraj R. Subbareddy, Mishali Naik, Alon Naveh, Abirami Prabhakaran, Eliezer Weissmann, David A. Koufaty, Paul Brett, Scott D. Hahn, Andrew J. Herdrich, Ravishankar Iyer, Nagabhushan Chitlur, Inder M. Sodhi, Gaurav Khanna, Russell J. Fenger
  • Patent number: 8751872
    Abstract: A system and method for handling exceptions in a multi-threaded computing environment. Information, such as that relating to an error state or pertaining to the propagation history of an exception, is stored in a separate object from the exception object itself. The separate propagation information object is accessible to the plurality of threads that are used to execute a user task. The separate object allows rich diagnostic information pertaining to the exception and its propagation through multiple threads to be presented to the developer of the software.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: June 10, 2014
    Assignee: Microsoft Corporation
    Inventors: Kumar Gaurav Khanna, Eric L. Eilebrecht, Melitta L. G. Andersen, Diana Milirud, Stephen H. Toub
  • Patent number: 8429454
    Abstract: Systems and methods are described for coordinating error reporting among a plurality of managed runtimes that are concurrently executing in the same process. In accordance with various embodiments, an error reporting manager that executes concurrently in the same process as the managed runtimes coordinates error reporting among the managed runtimes in a manner that does not require the managed runtimes to be aware of each other or to communicate directly with each other.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: April 23, 2013
    Assignee: Microsoft Corporation
    Inventors: Hsu-chieh Yuan, Richard M. Byers, Thomas Lai, Jon Langdon, Kumar Gaurav Khanna, Vipul D. Patel
  • Publication number: 20120304026
    Abstract: A system and method for handling exceptions in a multi-threaded computing environment. Information, such as that relating to an error state or pertaining to the propagation history of an exception, is stored in a separate object from the exception object itself. The separate propagation information object is accessible to the plurality of threads that are used to execute a user task. The separate object allows rich diagnostic information pertaining to the exception and its propagation through multiple threads to be presented to the developer of the software.
    Type: Application
    Filed: May 27, 2011
    Publication date: November 29, 2012
    Applicant: Microsoft Corporation
    Inventors: KUMAR GAURAV KHANNA, Eric L. Eilebrecht, Melitta L.G. Andersen, Diana Milirud, Stephen H. Toub
  • Patent number: 8074116
    Abstract: An exception notification system is described herein that provides an early notification that a software exception has occurred before exception handling code has run. The exception notification system receives a registration request from program code to register a handler to receive an early notification when an exception occurs. When an exception occurs, the system raises an event that calls each registered handler. After the handler returns, the system performs normal exception handling, so that the early notification does not change existing exception-handling behavior. The exception notification system allows a program to inspect and log an exception before the program state has been modified by exception handling. The program code can capture detailed information about the cause of the exception to enable further offline analysis. Thus, the exception notification system allows developers to improve their programs by receiving more information about unexpected conditions in the program code.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: December 6, 2011
    Assignee: Microsoft Corporation
    Inventors: Andrew J. Pardoe, Gaurav Khanna, Michael M. Magruder, Yi Lin, Jeffrey C. Schwartz
  • Publication number: 20110145662
    Abstract: Systems and methods are described for coordinating error reporting among a plurality of managed runtimes that are concurrently executing in the same process. In accordance with various embodiments, an error reporting manager that executes concurrently in the same process as the managed runtimes coordinates error reporting among the managed runtimes in a manner that does not require the managed runtimes to be aware of each other or to communicate directly with each other.
    Type: Application
    Filed: December 16, 2009
    Publication date: June 16, 2011
    Applicant: MICROSOFT CORPORATION
    Inventors: Hsu-chieh Yuan, Richard M. Byers, Thomas Lai, Jon Langdon, Kumar Gaurav Khanna, Vipul D. Patel
  • Publication number: 20110066847
    Abstract: Trust relationships in an online service system are established at a domain level, and propagated to components of domains as they attempt cross domain communication. In attempting to communicate across domains, a first component in a first domain attempts to validate a certificate of a second component in a second domain. Where the attempt to validate the certificate indicates that a trust relationship does not exist between the first component and the second domain, the first component determines whether a domain level trust relationship exists between the two domains. The first component propagates the trust status between the first and second domains to itself. If there is an existing trust relationship between the first and second domains, the first component validates the certificate of the second component in response. The second component executes the same process to complete the connection.
    Type: Application
    Filed: September 15, 2009
    Publication date: March 17, 2011
    Inventors: Aaron Christensen, William Browning, Gaurav Khanna, Sreekanth Vadapalli, Jatheen Anand
  • Publication number: 20100287414
    Abstract: An exception notification system is described herein that provides an early notification that a software exception has occurred before exception handling code has run. The exception notification system receives a registration request from program code to register a handler to receive an early notification when an exception occurs. When an exception occurs, the system raises an event that calls each registered handler. After the handler returns, the system performs normal exception handling, so that the early notification does not change existing exception-handling behavior. The exception notification system allows a program to inspect and log an exception before the program state has been modified by exception handling. The program code can capture detailed information about the cause of the exception to enable further offline analysis. Thus, the exception notification system allows developers to improve their programs by receiving more information about unexpected conditions in the program code.
    Type: Application
    Filed: May 6, 2009
    Publication date: November 11, 2010
    Applicant: Microsoft Corporation
    Inventors: Andrew J. Pardoe, Gaurav Khanna, Michael M. Magruder, Yi Lin, Jeffrey C. Schwartz
  • Publication number: 20100262814
    Abstract: An exception handling system is described herein that provides one or more distinguished classes of software exceptions that are handled differently than other exceptions. The system treats a distinguished exception as a “hard to catch” exception that is not passed to the catch block of program code unless a developer performs extra steps to acknowledge the distinguished nature of the exception and confirm that the program code is prepared to properly handle the exception. Exceptions that fall into this class are typically those that represent conditions from which normal exception handling practices cannot successfully recover, namely exceptions that corrupt application state. Accordingly, the system prevents the developer from catching these classes of exceptions by default unless the developer explicitly requests to have these exceptions delivered to the program code. Thus, the exception handling system encourages correct programming practices by preventing developer error by default.
    Type: Application
    Filed: April 10, 2009
    Publication date: October 14, 2010
    Applicant: Microsoft Corporation
    Inventors: Andrew J. Pardoe, Michael M. Magruder, Kumar Gaurav Khanna, Diana Milirud, Gaye Oncul Kok
  • Publication number: 20100218169
    Abstract: An error handling system is described herein that provides a facility for controlling the behavior of software when the software violates a contract condition. The system provides configurable runtime behavior that takes place when a contract fails. The error handling system provides an event that a hosting application or other software code can register to handle and that the system invokes upon detecting a contract failure. The application's response to the event determines how the system handles the failure. If the event is unhandled, the system triggers an escalation policy that allows an administrator or application to specify how the system handles contract failures. Thus, the error handling system provides increased control over the handling of contract failures within software code.
    Type: Application
    Filed: February 20, 2009
    Publication date: August 26, 2010
    Applicant: MICROSOFT CORPORATION
    Inventors: Melitta L. G. Andersen, Michael Barnett, Manuel A. Fahndrich, Brian M. Grunkemeyer, Katherine E. King, Michael M. Magruder, Andrew J. Pardoe, Kumar Gaurav Khanna