Abstract: A control unit for a plumbing assembly includes a first sensor for sensing a gesture and at least one direction associated with the gesture. The control unit also includes a first pair of sensors arranged along a first axis of the control unit, which determine a velocity of the gesture along the first axis. The control unit includes a second pair of sensors arranged a long a second axis of the control unit, which determine a velocity of the gesture along the second axis. The control unit includes at least one controller operably coupled to the first sensor, the first pair of sensors, and the second pair of sensors, where the at least one controller adjusts an operational state of the plumbing assembly based on the velocity of the gesture along the first axis, the velocity of the gesture along the second axis, and the at least one direction.

Abstract: Simulation of a circuit design using accelerated models can include determining, using computer hardware, that a design unit of a circuit design specified in a hardware description language is a prime block and determining, using the computer hardware, an output vector corresponding to an output of the prime block. Using the computer hardware, contents of the prime block can be replaced with an accelerated simulation model specified in a high level language, wherein the accelerated simulation model can determine a value for the output of the prime block as a function of values of one or more inputs of the prime block using the output vector. Using the computer hardware, the circuit design can be elaborated and compiled into object code that is executable to simulate the circuit design.

Abstract: Techniques for improved analysis and simulation of an IC design are disclosed. Simulation activity for an integrated circuit (IC) design is identified using one or more processors. One or more potential improvements to a simulation of the IC design are generated based on the simulation activity, the one or more potential improvements relating to at least one of signal activity or process activity, during simulation, reflected in the simulation activity. A hardware description language (HDL) design file corresponding to the IC design is modified to indicate the one or more potential improvements to the simulation.

Abstract: An egg boiler device for a refrigerator appliance is provided. In one aspect, a refrigerator appliance has a refrigerator door that defines a dispenser recess. The egg boiler device includes an end cap and a canister for receiving one or more eggs for cooking. The egg boiler device is positioned within the dispenser recess and the end cap is mounted to a dispenser assembly. A dispenser of the dispenser assembly directs a volume of heated water into the egg boiler device. The heated water imparts thermal energy to the eggs, and consequently, the eggs are cooked.

Abstract: A system and method are directed toward the synthesis of polymeric capsules using a phase inversion process by extrusion of polymeric droplets through a syringe-needle assembly or an iris-shutter mechanism. The polymeric solution may be prepared by dissolving PAN (polyacrylonitrile) polymer in DMF (Dimethyl Formamide) solvent at high temperature through continuous stirring. Following preparation of the capsules, further treatment was initiated using triethylamine in gelation bath to make the final product an efficient removal agent of water hardness.

Abstract: A pill dispenser includes a housing and a slidable drawer with a dispenser cup therein. A storage cup is fixed within the housing. The pill dispenser also includes a movable probe, a flexible tip on the probe, and a suction pump in fluid communication with the flexible tip. The pill dispenser may be configured for and/or methods of operating the pill dispenser may include rotating the probe a position above the storage cup, translating the probe downward into the storage cup, and activating the suction pump. While the suction pump is active, the probe is translated to the position above the storage cup, rotated to a position above the dispenser cup, and translated downward into the dispenser cup. The suction pump is deactivated when the flexible tip is within the dispenser cup.

Abstract: An egg boiler device for a refrigerator appliance is provided. In one aspect, a refrigerator appliance has a refrigerator door that defines a dispenser recess. The egg boiler device includes an end cap and a canister for receiving one or more eggs for cooking. The egg boiler device is positioned within the dispenser recess and the end cap is mounted to a dispenser assembly. A dispenser of the dispenser assembly directs a volume of heated water into the egg boiler device. The heated water imparts thermal energy to the eggs, and consequently, the eggs are cooked.

Abstract: A system and method are directed toward the synthesis of polymeric capsules using a phase inversion process by extrusion of polymeric droplets through a syringe-needle assembly or an iris-shutter mechanism. The polymeric solution may be prepared by dissolving PAN (polyacrylonitrile) polymer in DMF (Dimethyl Formamide) solvent at high temperature through continuous stirring. Following preparation of the capsules, further treatment was initiated using triethylamine in gelation bath to make the final product an efficient removal agent of water hardness.

Abstract: This application discloses a computing system configured to divide bins into primary bins and secondary bins based, at least in part, on a configuration of a circuit design describing an electronic device. The computing system can utilize the primary bins to record coverage events performed by the electronic device when modeled in a verification environment by the computing system, and infer coverage event records for the secondary bins based, at least in part, on the coverage event records for the primary bins.

Abstract: This application discloses a computing system to select a design block in a circuit design of an electronic device for functional verification result reuse based on isolating operational characteristics of the design block. The computing system can determine whether the selected design block was previously simulated with input stimulus. When the selected design block was previously simulated with the input stimulus, the computing system can bypass the simulation of the design block and utilize an output generated in the previous simulation of the selected design block in response to the input stimulus as a result for the simulation of the design block. When the selected design block was not previously simulated with the input stimulus, the computing system can simulate the selected design block with the input stimulus, and storing an output generated in the simulation of the selected design block for functional verification result reuse.

Abstract: This application discloses a design verification tool to generate an interconnect between portions of a circuit design in a mixed language environment. The design verification tool can select an interconnect generation technique based on characteristics for the portions of the circuit design and, during elaboration of the circuit design, utilize the selected interconnect generation technique to generate the interconnect. The design verification tool can generate the interconnect without the circuit design including code to identify the selected interconnect generation technique to the design verification tool. The design verification tool can perform functional verification operations on the elaborated circuit design, and modify results of the functional verification operations to remove an intermediate hierarchy utilized to generate the interconnect during elaboration. The modified results can show the portions of the circuit design being directly connected by the interconnect.

Abstract: This application discloses a computing system configured to determine that a first bind command is configured to prompt instantiation of an assertion module in a target module of a circuit design, which creates a mixed-language environment for the circuit design. The computing system, in response to the determination that the first bind command is configured to create the mixed-language environment for the circuit design, configured to generate a wrapper module configured to prompt instantiation of the assertion module in the wrapper module. The computing system configured to generate a second bind command configured to prompt instantiation of the wrapper module in the target module.

Abstract: This application discloses a computing system to select a design block in a circuit design of an electronic device for functional verification result reuse based on isolating operational characteristics of the design block. The computing system can determine whether the selected design block was previously simulated with input stimulus. When the selected design block was previously simulated with the input stimulus, the computing system can bypass the simulation of the design block and utilize an output generated in the previous simulation of the selected design block in response to the input stimulus as a result for the simulation of the design block. When the selected design block was not previously simulated with the input stimulus, the computing system can simulate the selected design block with the input stimulus, and storing an output generated in the simulation of the selected design block for functional verification result reuse.

Abstract: This application discloses a design verification tool to generate an interconnect between portions of a circuit design in a mixed language environment. The design verification tool can select an interconnect generation technique based on characteristics for the portions of the circuit design and, during elaboration of the circuit design, utilize the selected interconnect generation technique to generate the interconnect. The design verification tool can generate the interconnect without the circuit design including code to identify the selected interconnect generation technique to the design verification tool. The design verification tool can perform functional verification operations on the elaborated circuit design, and modify results of the functional verification operations to remove an intermediate hierarchy utilized to generate the interconnect during elaboration. The modified results can show the portions of the circuit design being directly connected by the interconnect.

Abstract: This application discloses a computing system configured to divide bins into primary bins and secondary bins based, at least in part, on a configuration of a circuit design describing an electronic device. The computing system can utilize the primary bins to record coverage events performed by the electronic device when modeled in a verification environment by the computing system, and infer coverage event records for the secondary bins based, at least in part, on the coverage event records for the primary bins.

Abstract: This application discloses a computing system configured to determine that a first bind command is configured to prompt instantiation of an assertion module in a target module of a circuit design, which creates a mixed-language environment for the circuit design. The computing system, in response to the determination that the first bind command is configured to create the mixed-language environment for the circuit design, configured to generate a wrapper module configured to prompt instantiation of the assertion module in the wrapper module. The computing system configured to generate a second bind command configured to prompt instantiation of the wrapper module in the target module.