Patents by Inventor Gaurav Mehta

Gaurav Mehta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stacked Die Packages
    Publication number: 20080054435
    Abstract: A stacked die semiconductor package that includes a substrate with a plurality of adhesive portions arranged in a manner to create at least one gap between the adhesive portions. The package also includes a first semiconductor chip having a non-active surface in contact with the adhesive portions, and an active surface being electrically connected to the substrate. In the package, a second semiconductor chip the non-active surface of the second semiconductor chip is attached to the non-active surface of the first semiconductor chip by a layer of adhesive therebetween. The active surface of the second semiconductor chip is electrically connected to the substrate. An encapsulant material covers the first and second semiconductor chips and their associated electrical connections. The encapsulating material fills the at least one gap between the plurality of adhesive portions and thereby encapsulates the second semiconductor chip and its associated electrical connection.
    Type: Application
    Filed: August 29, 2007
    Publication date: March 6, 2008
    Applicant: United Test and Assembly Center, Ltd.
    Inventors: Gaurav MEHTA, Hien Boon Tan, Susanto Tanary, Mary Annie Cheong, Anthony Sun, Chuen Wang
  • Low power precharge scheme for memory bit lines
    Patent number: 6631093
    Abstract: A low power memory bit line precharge scheme. A memory bit line is coupled to a first read precharge device. A second write precharge device is also coupled to the memory bit line and is to be enabled only in response to a memory write operation. The first read and second write precharge devices are sized such that their combined drive strength is sufficient to precharge the first memory bit line during a precharge period following a write operation.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: October 7, 2003
    Assignee: Intel Corporation
    Inventors: Sudarshan Kumar, Jiann-Cherng Lan, Wenjie Jiang, Gaurav Mehta, Sadhana Madhyastha
  • Method and apparatus for low power domino decoding
    Patent number: 6593776
    Abstract: A decoder includes multiple decode gates, each to provide one bit of a decoded output signal. At least two of the decode gates share a transistor. According to one aspect, each of the multiple decode gates is a skewed gate.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: July 15, 2003
    Assignee: Intel Corporation
    Inventors: Sudarshan Kumar, Gaurav Mehta, Vivek Joshi
  • Method and apparatus for low power domino decoding
    Publication number: 20030025531
    Abstract: A decoder includes multiple decode gates, each to provide one bit of a decoded output signal. At least two of the decode gates share a transistor. According to one aspect, each of the multiple decode gates is a skewed gate.
    Type: Application
    Filed: August 3, 2001
    Publication date: February 6, 2003
    Inventors: Sudarshan Kumar, Gaurav Mehta, Vivek Joshi
  • LOW POWER PRECHARGE SCHEME FOR MEMORY BIT LINES
    Publication number: 20030002382
    Abstract: A low power memory bit line precharge scheme. A memory bit line is coupled to a first read precharge device. A second write precharge device is also coupled to the memory bit line and is to be enabled only in response to a memory write operation.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 2, 2003
    Inventors: Sudarshan Kumar, Jiann-Cherng Lan, Wenjie Jiang, Gaurav Mehta, Sadhana Madhyastha