Abstract: A machine learning (ML) model is described herein that predicts computational resource requirements (e.g., a memory and/or runtime metric) for evaluating an integrated circuit (IC) design (e.g., static verification) based on design features extracted from the IC design and auxiliary features related to the IC design. The model may be used to predict the metric for sub-blocks of the IC design. A platform selector may select one of multiple platforms on which to evaluate the IC design or sub-blocks of the IC design based on the predicted metric(s) and specifications of the platforms. The model may be trained to correlate a combination of design features extracted from training IC designs and auxiliary features related to the training IC designs, with metrics of computational resources used in evaluation of the training IC designs, such as with a multiple-linear-regression-based supervised learning technique.

Abstract: A system performs efficient verification of a circuit design. The system receives a circuit design including circuit blocks. The system identifies some of the circuit blocks as modeled circuit blocks. The system generates simplified reduced models (SRMs) for the modeled circuit blocks. A simplified reduced model includes circuit details sufficient for static verification of the circuit design but excludes some of the circuit details for the modeled circuit block. The system performs static verification of the circuit design using the simplified reduced models.

Abstract: State table complexity reduction in a hierarchical verification flow is provided by identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the power supplies provide outputs to or receive inputs from circuity external to the hierarchical group; merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical group to create a merged power state table for the hierarchical group; removing, by a processing device, any power states associated with the non-peripheral supplies from the merged power state table to create a reduced power state table; and modeling a reduced logical block based on the reduced power state table.

Abstract: State table complexity reduction in a hierarchical verification flow is provided by identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the power supplies provide outputs to or receive inputs from circuity external to the hierarchical group; merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical group to create a merged power state table for the hierarchical group; removing, by a processing device, any power states associated with the non-peripheral supplies from the merged power state table to create a reduced power state table; and modeling a reduced logical block based on the reduced power state table.