Abstract: Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.

Abstract: Various implementations described herein are directed to a device having memory with an array of bitcells arranged in columns and rows, wherein a first number of columns represents a first number of output bits, and a second number of columns represents a second number of output bits. The device may include dummy wordline (DWL) circuitry having multiple DWL paths including a first DWL path disposed along the first number of columns and a second DWL path disposed along the second number of columns. The first DWL path has a shorter length than the second DWL path so as to allow for faster operation of the bitcells in the memory associated with the first number of output bits.

Abstract: Various implementations described herein are directed to a device having memory with an array of bitcells arranged in columns and rows, wherein a first number of columns represents a first number of output bits, and a second number of columns represents a second number of output bits. The device may include dummy wordline (DWL) circuitry having multiple DWL paths including a first DWL path disposed along the first number of columns and a second DWL path disposed along the second number of columns. The first DWL path has a shorter length than the second DWL path so as to allow for faster operation of the bitcells in the memory associated with the first number of output bits.

Abstract: Various implementations described herein are directed to a device having an array of bitcells with bitlines coupled to columns of the bitcells. The device may include one or more switch structures that are coupled between the bitlines and a supply voltage, and the switch structures may be configured to precharge the bitlines to the supply voltage when activated. In some instances, the supply voltage may refer to ground or a ground related voltage having a voltage near or equal to zero volts (0V).

Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry having multiple banks of bitcell arrays including a first pair of bank arrays and a second pair of bank arrays. The first pair of bank arrays may have a first number of rows, and the second pair of bank arrays have a second number of rows that is different than the first number of rows. The integrated circuit may include bank multiplexer circuitry that is coupled to the first pair of bank arrays via a first channel and the second pair of bank arrays via a second channel that is separate from the first channel. The bank multiplexer circuitry may provide an output data signal from the first pair of bank arrays or the second pair of bank arrays based on a control signal.

Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry having multiple banks of bitcell arrays including a first pair of bank arrays and a second pair of bank arrays. The first pair of bank arrays may have a first number of rows, and the second pair of bank arrays have a second number of rows that is different than the first number of rows. The integrated circuit may include bank multiplexer circuitry that is coupled to the first pair of bank arrays via a first channel and the second pair of bank arrays via a second channel that is separate from the first channel. The bank multiplexer circuitry may provide an output data signal from the first pair of bank arrays or the second pair of bank arrays based on a control signal.

Abstract: Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.