Patents by Inventor Gaurav Shukla

Gaurav Shukla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230052288
    Abstract: An improved UAV system and methods for operation in an inventory management system. The methods include generating a three dimensional (3D) map and estimating a position and orientation of the UAV based upon this map; autonomously navigating the UAV in the environment by using the generated 3d map in conjunction with the position and the orientation of the UAV; performing static and dynamic obstacle avoidance in the environment using collision avoidance; and finding the optimal path from a source node to a destination node within the environment.
    Type: Application
    Filed: August 9, 2022
    Publication date: February 16, 2023
    Applicant: DIGIT7 INDIA PRIVATE LIMITED
    Inventors: Chithrai Selvakumar Mani, Gaurav Shukla
  • Patent number: 7650454
    Abstract: An arbiter module receives two or more closely occurring asynchronous requests and provides an output with a low metastability failure probability. The arbiter module includes a request resolving module that receives multiple asynchronous requests for providing a final output. The request resolving module includes one or more arbiter stages cascaded with each other and operatively coupled with logic units.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: January 19, 2010
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventors: Gaurav Shukla, Piyush Jain
  • Publication number: 20090113099
    Abstract: An arbiter module receives two or more closely occurring asynchronous requests and provides an output with a low metastability failure probability. The arbiter module includes a request resolving module that receives multiple asynchronous requests for providing a final output. The request resolving module includes one or more arbiter stages cascaded with each other and operatively coupled with logic units.
    Type: Application
    Filed: October 26, 2007
    Publication date: April 30, 2009
    Applicant: STMICROELECTRONICS PVT. LTD.
    Inventors: Gaurav SHUKLA, Plyush JAIN