Patents by Inventor Gaurav Singh

Gaurav Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210160774
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may determine that a condition associated with failure of a cell acquisition procedure is satisfied; output a notification that permits a user of the UE to provide input indicating whether to deactivate one or more radio frequency components of the UE based at least in part on determining that the condition associated with failure of the cell acquisition procedure is satisfied; receive user input that indicates whether to deactivate the one or more radio frequency components of the UE based at least in part on outputting the notification; and selectively deactivate the one or more radio frequency components of the UE based at least in part on the user input. Numerous other aspects are provided.
    Type: Application
    Filed: November 22, 2019
    Publication date: May 27, 2021
    Inventors: Nitish NAGAR, Swaroop Singh KSHATRIYA, Gaurav SINGH, Amit Kumar SINGH
  • Patent number: 10921836
    Abstract: Voltage regulators with fast transient response are provided herein. According to one aspect, a voltage regulator for accepting an input voltage (VREF) and producing an output voltage (VOUT) includes an operational amplifier having as a first input (VREF) and having as a second input a feedback voltage (VFB); an output amplifier having an input coupled to the output of the operational amplifier and an output that produces VOUT, the output being coupled to a feedback path that produces VFB; a compensation capacitor (Cc) connected between the output of the output amplifier and an input to a buffer amplifier that supplies a voltage to the input of the output amplifier. The buffer amplifier has a transconductance (gmBUF) that is controlled to be proportional to a load current (ILOAD), thereby causing the left hand plane zero of the buffer amplifier to cancel the pole created by the output amplifier.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: February 16, 2021
    Assignee: Qorvo US, Inc.
    Inventor: Gaurav Singh
  • Patent number: 10917305
    Abstract: A method and system for conducting audit for an assessment platform is provided. The disclosure provides an automated audit process that will guarantee the computer systems along with the network will hold well during the course of the online examination. The system mainly comprises a primary server checking module and a captivation module. The primary server checking module is configured to perform the system level, browser level, network level and bandwidth level tests to ensure better risk management and reflect the exact capacity of the online examination center. A network congestion will also be built for a prolonged duration of time. The captivation module is gateway for deploying different local instance solutions. The restrictions it will impose will prevent any sort of malpractice (from remote agents as well) and optimize the use of CPU and memory to bring forth best performance of the system during the course of the exam.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: February 9, 2021
    Assignee: Tata Consultancy Services Limited
    Inventors: Viral Prakash Shah, Abhirup Das, Gaurav Singh, Neeta Jasvindersingh Kabo
  • Patent number: 10917758
    Abstract: Techniques for enabling a system to create a multimedia messaging service (MMS) message or a short message service (SMS) message from a spoken message are described. A system may receive audio data corresponding to a spoken message. The system may determine a recipient of the spoken message as well as a device associated with the recipient. The system may determine the type of messaging supported by the device. Based on the messaging capabilities, the system generates either a MMS message or a SMS message. The MMS message may include a message payload including a portion of text corresponding to content of the message as well as audio data embedded in the message payload. The SMS message may include a message payload including a portion of text corresponding to content of the message as well as a link to message content audio data stored by the system.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: February 9, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Brandon Taylor, Gaurav Singh, Reza Abdollahi, Mugunthan Govindaraju
  • Patent number: 10893070
    Abstract: An online system maintains pages and accesses a graph of nodes representing the pages. Each node is labeled to indicate that a corresponding page is for a real-world entity, an imposter of the real-world entity, or a derived entity complying with or violating a policy. The online system retrieves machine-learning models, each of which is trained based on labels for a set of the nodes and features of corresponding pages. A first model predicts whether a page is for a derived entity based on features of the page. Responsive to predicting the page is not for a derived entity, a second model predicts whether the page is for a real-world entity or an imposter based on features of the page. Responsive to predicting the page is for a derived entity, a third model predicts whether the derived entity complies with or violates the policy based on features of the page.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: January 12, 2021
    Assignee: Facebook, Inc.
    Inventors: Haotian Wang, Komal Kapoor, Gaurav Singh Thakur
  • Publication number: 20200336509
    Abstract: An online system maintains pages and accesses a graph of nodes representing the pages. Each node is labeled to indicate that a corresponding page is for a real-world entity, an imposter of the real-world entity, or a derived entity complying with or violating a policy. The online system retrieves machine-learning models, each of which is trained based on labels for a set of the nodes and features of corresponding pages. A first model predicts whether a page is for a derived entity based on features of the page. Responsive to predicting the page is not for a derived entity, a second model predicts whether the page is for a real-world entity or an imposter based on features of the page. Responsive to predicting the page is for a derived entity, a third model predicts whether the derived entity complies with or violates the policy based on features of the page.
    Type: Application
    Filed: April 18, 2019
    Publication date: October 22, 2020
    Inventors: Haotian Wang, Komal Kapoor, Gaurav Singh Thakur
  • Patent number: 10719452
    Abstract: An example programmable integrated circuit (IC) includes a processing system having a processor, a master circuit, and a system memory management unit (SMMU). The SMMU includes a first translation buffer unit (TBU) coupled to the master circuit, an address translation (AT) circuit, an AT interface coupled to the AT circuit, and a second TBU coupled to the AT circuit, and programmable logic coupled to the AT circuit in the SMMU through the AT interface.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: July 21, 2020
    Assignee: XILINX, INC.
    Inventors: Ygal Arbel, Sagheer Ahmad, Gaurav Singh
  • Patent number: 10594663
    Abstract: This disclosure relates generally to computer based assessments, and more particularly to secured assessment distribution and printing. In one embodiment, the method includes mapping an assessment metadata with assessment conduction center (ACC) data to identify drive data having ACC location associated with candidates, count of candidates for each subject assessment, and subjects mapping with respective ACCs. The subjects are mapped with prestored content creator profile data to identify content creators capable of creating content for question papers corresponding to assessment subjects. The content for the question papers is bundled into distinct bundles that are encrypted with an encryption key based on schedule of assessment of assessment subject. The bundles are mapped with the drive data to identify bundles for respective ACCs and candidate profiles.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: March 17, 2020
    Assignee: Tata Consultancy Services Limited
    Inventors: Viral Prakash Shah, Rakesh Ramesh Ahirrao, Gaurav Singh, Komal Rameshwar Balode
  • Patent number: 10594135
    Abstract: An object of the disclosure is to provide a compact RC triggered ESD clamp, which is used for fast ramp supplies, and is immune to parasitics, process, temperature variations, and a noisy environment. A further object of the disclosure is to provide an ESD clamp circuit with low power consumption, and which is robust against reliability or burnout failures. A further object of the disclosure is that the short time constant and the long time constant are realized using a single capacitor, charged by two separate resistors. Still further, another object of the disclosure is that the elements are connected in such a way that there are no additional active junctions connected to the charging node of the ESD clamp.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: March 17, 2020
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Gaurav Singh
  • Publication number: 20200073420
    Abstract: Voltage regulators with fast transient response are provided herein. According to one aspect, a voltage regulator for accepting an input voltage (VREF) and producing an output voltage (VOUT) comprises an operational amplifier having as a first input (VREF) and having as a second input a feedback voltage (VFB); an output amplifier having an input coupled to the output of the operational amplifier and an output that produces VOUT, the output being coupled to a feedback path that produces VFB; a compensation capacitor (Cc) connected between the output of the output amplifier and an input to a buffer amplifier that supplies a voltage to the input of the output amplifier. The buffer amplifier has a transconductance (gmBUF) that is controlled to be proportional to a load current (ILOAD), thereby causing the left hand plane zero of the buffer amplifier to cancel the pole created by the output amplifier.
    Type: Application
    Filed: November 8, 2019
    Publication date: March 5, 2020
    Inventor: Gaurav Singh
  • Patent number: 10534385
    Abstract: Voltage regulators with fast transient response are provided herein. According to one aspect, a voltage regulator for accepting an input voltage (VREF) and producing an output voltage (VouT) includes an operational amplifier having as a first input (VREF) and having as a second input a feedback voltage (VFB); an output amplifier having an input coupled to the output of the operational amplifier and an output that produces VOUT, the output being coupled to a feedback path that produces VFB; a compensation capacitor (Cc) connected between the output of the output amplifier and an input to a buffer amplifier that supplies a voltage to the input of the output amplifier. The buffer amplifier has a transconductance (gmBUF) that is controlled to be proportional to a load current (ILOAD), thereby causing the left hand plane zero of the buffer amplifier to cancel the pole created by the output amplifier.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: January 14, 2020
    Assignee: Qorvo US, Inc.
    Inventor: Gaurav Singh
  • Publication number: 20190391929
    Abstract: An example programmable integrated circuit (IC) includes a processing system having a processor, a master circuit, and a system memory management unit (SMMU). The SMMU includes a first translation buffer unit (TBU) coupled to the master circuit, an address translation (AT) circuit, an AT interface coupled to the AT circuit, and a second TBU coupled to the AT circuit, and programmable logic coupled to the AT circuit in the SMMU through the AT interface.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 26, 2019
    Applicant: Xilinx, Inc.
    Inventors: Ygal Arbel, Sagheer Ahmad, Gaurav Singh
  • Patent number: 10467306
    Abstract: A method and system is provided for user authorization based information search and access. The present application provides a bandwidth efficient method and system for searching and accessing information based on a user authorization within an enterprise resource planning (ERP) environment by authorizing the user for searching and accessing the information containing authorization key ingrained therein without compromising speed of searching, comprises inputting user defined search query for information within the enterprise resource planning environment; forming user defined search query by incorporating authorization information of the user therein; searching a plurality of indexes for information; extracting search results from the plurality of indexes; and displaying the extracted search results.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: November 5, 2019
    Assignee: Tata Consultancy Services Limited
    Inventors: Viral Prakash Shah, Gaurav Singh, Aakash Khandelwal, Sourabh Sanyal
  • Publication number: 20190164524
    Abstract: A technique for selecting locations of tear lines when displaying visual content. The technique includes receiving coordinates for one or more portions of a display where a tear is permitted and determining if a frame transition is to occur while rendered content is being scanned out for display within the one or more portions of the display where tear is permitted. If the frame transition is to occur while the scanline for the display is in the one or more portions of the display where tear is permitted, then the technique further includes allowing the frame transition to occur. If the frame transition is to occur while the scanline for the display is not in the one or more portions of the display where tear is permitted, then the technique further includes delaying the frame transition until at least when the scanline for the display is in the one or more portions of the display where tear is permitted.
    Type: Application
    Filed: July 6, 2018
    Publication date: May 30, 2019
    Inventors: Radhika Ranjan SONI, Gaurav SINGH
  • Patent number: 10191868
    Abstract: Proving for a framework for propagating priorities to a memory subsystem in a computing system environment is disclosed herein. By way of example, a memory access handler is provided for managing memory access requests and determining associated priorities. The memory access handler includes logic configured for propagating memory requests and the associated priorities to lower levels of a computer hierarchy. A memory subsystem receives the memory access requests and the priorities.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: January 29, 2019
    Assignee: AMPERE COMPUTING LLC
    Inventors: Kjeld Svendsen, Millind Mittal, Gaurav Singh
  • Patent number: 10176739
    Abstract: An aspect of the present invention proposes a method for performing partial refresh on display panels. According to one or more embodiments of the present invention, the display panels may be implemented as self-refreshing display panels communicatively coupled with a computing device that generates graphical data for display in the display panel. To perform partial refresh, consecutive frames are compared to identify the portions of the frames with updated material. In one or more embodiments, only the pixels corresponding to the updated portion(s) are refreshed in the display panel.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: January 8, 2019
    Assignee: Nvidia Corporation
    Inventors: Gaurav Singh, Radhika Ranjan Soni
  • Publication number: 20190006841
    Abstract: An object of the disclosure is to provide a compact RC triggered ESD clamp, which is used for fast ramp supplies, and is immune to parasitics, process, temperature variations, and a noisy environment. A further object of the disclosure is to provide an ESD clamp circuit with low power consumption, and which is robust against reliability or burnout failures. A further object of the disclosure is that the short time constant and the long time constant are realized using a single capacitor, charged by two separate resistors. Still further, another object of the disclosure is that the elements are connected in such a way that there are no additional active junctions connected to the charging node of the ESD clamp.
    Type: Application
    Filed: June 29, 2017
    Publication date: January 3, 2019
    Inventor: Gaurav Singh
  • Publication number: 20180287880
    Abstract: A method and system for conducting audit for an assessment platform is provided. The disclosure provides an automated audit process that will guarantee the computer systems along with the network will hold well during the course of the online examination. The system mainly comprises a primary server checking module and a captivation module. The primary server checking module is configured to perform the system level, browser level, network level and bandwidth level tests to ensure better risk management and reflect the exact capacity of the online examination center. A network congestion will also be built for a prolonged duration of time. The captivation module is gateway for deploying different local instance solutions. The restrictions it will impose will prevent any sort of malpractice (from remote agents as well) and optimize the use of CPU and memory to bring forth best performance of the system during the course of the exam.
    Type: Application
    Filed: November 3, 2017
    Publication date: October 4, 2018
    Applicant: Tata Consultancy Services Limited
    Inventors: Viral Prakash Shah, Abhirup Das, Gaurav Singh, Neeta Jasvindersingh Kabo
  • Publication number: 20180203810
    Abstract: Proving for a framework for propagating priorities to a memory subsystem in a computing system environment is disclosed herein. By way of example, a memory access handler is provided for managing memory access requests and determining associated priorities. The memory access handler includes logic configured for propagating memory requests and the associated priorities to lower levels of a computer hierarchy. A memory subsystem receives the memory access requests and the priorities.
    Type: Application
    Filed: March 12, 2018
    Publication date: July 19, 2018
    Inventors: Kjeld Svendsen, Millind Mittal, Gaurav Singh
  • Publication number: 20180173258
    Abstract: Voltage regulators with fast transient response are provided herein. According to one aspect, a voltage regulator for accepting an input voltage (VREF) and producing an output voltage (VOUT) comprises an operational amplifier having as a first input (VREF) and having as a second input a feedback voltage (VFB); an output amplifier having an input coupled to the output of the operational amplifier and an output that produces VOUT, the output being coupled to a feedback path that produces VFB; a compensation capacitor (Cc) connected between the output of the output amplifier and an input to a buffer amplifier that supplies a voltage to the input of the output amplifier. The buffer amplifier has a transconductance (gmBUF) that is controlled to be proportional to a load current (ILOAD), thereby causing the left hand plane zero of the buffer amplifier to cancel the pole created by the output amplifier.
    Type: Application
    Filed: December 19, 2017
    Publication date: June 21, 2018
    Inventor: Gaurav Singh