Abstract: Technologies for providing precise peak-to-peak amplitude detection for harmonic-rich circuits are described. A peak-to-peak amplitude detector circuit can include a peak-to-peak rectifier and a linear combiner. The peak-to-peak rectifier can rectify a positive peak and a negative peak of an incoming analog signal to obtain a positive and a negative rectified signal. The linear combiner can combine and compare the positive and negative rectified signals and positive and negative target signals to obtain an output signal indicative of a peak-to-peak amplitude of the incoming analog signal.

Abstract: This disclosure relates to a receiver that includes a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.

Abstract: This disclosure relates to a receiver comprising a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.

Abstract: This disclosure relates to a receiver comprising a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.