Patents by Inventor Gauri V. Karve
Gauri V. Karve has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160163707Abstract: Embodiments of the present invention provide a method for epitaxially growing a FinFET. One method may include providing a semiconductor substrate including an insulator and an underlayer; forming a channel layer on the semiconductor substrate using epitaxial growth; etching a recess into the channel layer and epitaxially regrowing a portion on the channel layer; etching the channel layer and the underlayer to form fins; forming a gate structure and a set of spacers; etching a source drain region into the channel layer; and forming a source drain material in the source drain region.Type: ApplicationFiled: February 5, 2016Publication date: June 9, 2016Inventors: Kangguo Cheng, Eric C.T. Harley, Judson R. Holt, Gauri V. Karve, Yue Ke, Derrick Liu, Timothy J. McArdle, Shogo Mochizuki, Alexander Reznicek, Melissa Alyson Smith
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Patent number: 9362280Abstract: An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.Type: GrantFiled: May 13, 2013Date of Patent: June 7, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Gauri V. Karve, Mark D. Hall, Srikanth B. Samavedam
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Patent number: 9287264Abstract: Embodiments of the present invention provide a method for epitaxially growing a FinFET. One method may include providing a semiconductor substrate including an insulator and an underlayer; forming a channel layer on the semiconductor substrate using epitaxial growth; etching a recess into the channel layer and epitaxially regrowing a portion on the channel layer; etching the channel layer and the underlayer to form fins; forming a gate structure and a set of spacers; etching a source drain region into the channel layer; and forming a source drain material in the source drain region.Type: GrantFiled: December 5, 2014Date of Patent: March 15, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Kangguo Cheng, Eric C. T. Harley, Judson R. Holt, Gauri V. Karve, Yue Ke, Derrick Liu, Timothy J. McArdle, Shogo Mochizuki, Alexander Reznicek, Melissa A. Smith
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Publication number: 20130249015Abstract: An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.Type: ApplicationFiled: May 13, 2013Publication date: September 26, 2013Applicant: Freescale Semiconductor, Inc.Inventors: Gauri V. Karve, Mark D. Hall, Srikanth B. Samavedam
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Patent number: 8460996Abstract: An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.Type: GrantFiled: October 31, 2007Date of Patent: June 11, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Gauri V. Karve, Mark D. Hall, Srikanth B. Samavedam
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Patent number: 8017469Abstract: A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices (50, 52) and core transistor devices (51, 53) on a single substrate (15) having a silicon germanium channel layer (21) in the PMOS device areas (112, 113), where each DGO transistor device (50, 52) includes a metal gate (25), an upper gate oxide region (60, 84) formed from a second, relatively higher high-k metal oxide layer (24), and a lower gate oxide region (58, 84) formed from a first relatively lower high-k layer (22), and where each core transistor device (51, 53) includes a metal gate (25) and a core gate dielectric layer (72, 98) formed from only the second, relatively higher high-k metal oxide layer (24).Type: GrantFiled: January 21, 2009Date of Patent: September 13, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Tien-Ying Luo, Gauri V. Karve, Daniel G. Tekleab
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Patent number: 7790528Abstract: A semiconductor process and apparatus provide a planarized hybrid substrate (15) by thermally oxidizing SOI sidewalls (90) in a trench opening (93) to form SOI sidewall oxide spacers (94) which are trimmed while etching through a buried oxide layer (80) to expose the underlying bulk substrate (70) for subsequent epitaxial growth of an epitaxial semiconductor layer (96).Type: GrantFiled: May 1, 2007Date of Patent: September 7, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Gregory S. Spencer, John M. Grant, Gauri V. Karve
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Publication number: 20100184260Abstract: A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices (50, 52) and core transistor devices (51, 53) on a single substrate (15) having a silicon germanium channel layer (21) in the PMOS device areas (112, 113), where each DGO transistor device (50, 52) includes a metal gate (25), an upper gate oxide region (60, 84) formed from a second, relatively higher high-k metal oxide layer (24), and a lower gate oxide region (58, 84) formed from a first relatively lower high-k layer (22), and where each core transistor device (51, 53) includes a metal gate (25) and a core gate dielectric layer (72, 98) formed from only the second, relatively higher high-k metal oxide layer (24).Type: ApplicationFiled: January 21, 2009Publication date: July 22, 2010Inventors: Tien-Ying Luo, Gauri V. Karve, Daniel G. Tekleab
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Patent number: 7749829Abstract: A semiconductor process and apparatus provides a planarized hybrid substrate (16) by removing a nitride mask layer (96) and using an oxide polish stop layer (92) when an epitaxial semiconductor layer (99) is being polished for DSO and BOS integrations. To this end, an initial SOI wafer semiconductor stack (11) is formed which includes one or more oxide polish stop layers (91, 92) formed between the SOI semiconductor layer (90) and a nitride mask layer (93). The oxide polish stop layer (92) may be formed by depositing a densified LPCVD layer of TEOS to a thickness of approximately 100-250 Angstroms.Type: GrantFiled: May 1, 2007Date of Patent: July 6, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Gauri V. Karve, Debby Eades, Gregory S. Spencer, Ted R. White
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Patent number: 7709331Abstract: A method of forming devices including forming a first region and a second region in a semiconductor substrate is provided. The method further includes forming a semiconductive material over the first region, wherein the semiconductive material has a different electrical property than the first semiconductor substrate, forming a first dielectric material over the first region, depositing a second dielectric material over the first dielectric material and over the second region, wherein the second dielectric material is different than the first dielectric material, and depositing a gate electrode material over the high dielectric constant material. In one embodiment, the semiconductive material is silicon germanium and the semiconductor substrate is silicon.Type: GrantFiled: September 7, 2007Date of Patent: May 4, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Gauri V. Karve, Srikanth B. Samavedam, William J. Taylor, Jr.
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Patent number: 7666730Abstract: A method for forming a semiconductor structure includes forming a channel region layer over a semiconductor layer where the semiconductor layer includes a first and a second well region, forming a protection layer over the channel region layer, forming a first gate dielectric layer over the first well region, forming a first metal gate electrode layer over the first gate dielectric, removing the protection layer, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer over the second gate dielectric layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and the first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and the second metal gate electrode layer over the channel region layer.Type: GrantFiled: June 29, 2007Date of Patent: February 23, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Gauri V. Karve, Cristiano Capasso, Srikanth B. Samavedam, James K. Schaeffer, William J. Taylor, Jr.
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Publication number: 20090108296Abstract: An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.Type: ApplicationFiled: October 31, 2007Publication date: April 30, 2009Inventors: Gauri V. Karve, Mark D. Hall, Srikanth B. Samavedam
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Publication number: 20090068807Abstract: A method of forming devices including forming a first region and a second region in a semiconductor substrate is provided. The method further includes forming a semiconductive material over the first region, wherein the semiconductive material has a different electrical property than the first semiconductor substrate, forming a first dielectric material over the first region, depositing a second dielectric material over the first dielectric material and over the second region, wherein the second dielectric material is different than the first dielectric material, and depositing a gate electrode material over the high dielectric constant material. In one embodiment, the semiconductive material is silicon germanium and the semiconductor substrate is silicon.Type: ApplicationFiled: September 7, 2007Publication date: March 12, 2009Inventors: Gauri V. Karve, Srikanth B. Samavedam, William J. Taylor, JR.
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Publication number: 20090004792Abstract: A method for forming a semiconductor structure includes forming a channel region layer over a semiconductor layer where the semiconductor layer includes a first and a second well region, forming a protection layer over the channel region layer, forming a first gate dielectric layer over the first well region, forming a first metal gate electrode layer over the first gate dielectric, removing the protection layer, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer over the second gate dielectric layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and the first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and the second metal gate electrode layer over the channel region layer.Type: ApplicationFiled: June 29, 2007Publication date: January 1, 2009Inventors: Gauri V. Karve, Cristiano Capasso, Srikanth B. Samavedam, James K. Schaeffer, William J. Taylor, JR.
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Publication number: 20080274595Abstract: A semiconductor process and apparatus provide a planarized hybrid substrate (15) by thermally oxidizing SOI sidewalls (90) in a trench opening (93) to form SOI sidewall oxide spacers (94) which are trimmed while etching through a buried oxide layer (80) to expose the underlying bulk substrate (70) for subsequent epitaxial growth of an epitaxial semiconductor layer (96).Type: ApplicationFiled: May 1, 2007Publication date: November 6, 2008Inventors: Gregory S. Spencer, John M. Grant, Gauri V. Karve
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Publication number: 20080274594Abstract: A semiconductor process and apparatus provides a planarized hybrid substrate (16) by removing a nitride mask layer (96) and using an oxide polish stop layer (92) when an epitaxial semiconductor layer (99) is being polished for DSO and BOS integrations. To this end, an initial SOI wafer semiconductor stack (11) is formed which includes one or more oxide polish stop layers (91, 92) formed between the SOI semiconductor layer (90) and a nitride mask layer (93). The oxide polish stop layer (92) may be formed by depositing a densified LPCVD layer of TEOS to a thickness of approximately 100-250 Angstroms.Type: ApplicationFiled: May 1, 2007Publication date: November 6, 2008Inventors: Gauri V. Karve, Debby Eades, Gregory S. Spencer, Ted R. White
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Patent number: 7445981Abstract: A method includes forming a first gate dielectric layer over a semiconductor layer having a first and a second well region, forming a first metal gate electrode layer over the first gate dielectric, forming a sidewall protection layer over the first metal gate electrode layer and adjacent sidewalls of the first gate dielectric layer and first metal gate electrode layer, forming a channel region layer over the second well region, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and second metal gate electrode layer over the channel region layer and over the second well region.Type: GrantFiled: June 29, 2007Date of Patent: November 4, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Gauri V. Karve, Cristiano Capasso, Srikanth B. Samavedam, James K. Schaeffer, William J. Taylor, Jr.
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Patent number: RE45955Abstract: A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices (50, 52) and core transistor devices (51, 53) on a single substrate (15) having a silicon germanium channel layer (21) in the PMOS device areas (112, 113), where each DGO transistor device (50, 52) includes a metal gate (25), an upper gate oxide region (60, 84) formed from a second, relatively higher high-k metal oxide layer (24), and a lower gate oxide region (58, 84) formed from a first relatively lower high-k layer (22), and where each core transistor device (51, 53) includes a metal gate (25) and a core gate dielectric layer (72, 98) formed from only the second, relatively higher high-k metal oxide layer (24).Type: GrantFiled: August 6, 2014Date of Patent: March 29, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Tien Ying Luo, Gauri V. Karve, Daniel K. Tekleab