Patents by Inventor Gautam B. Doshi
Gautam B. Doshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9552205Abstract: A processor including a decode unit to receive a vector indexed load plus arithmetic and/or logical (A/L) operation plus store instruction. The instruction is to indicate a source packed memory indices operand that is to have a plurality of packed memory indices. The instruction is also to indicate a source packed data operand that is to have a plurality of packed data elements. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to load a plurality of data elements from memory locations corresponding to the plurality of packed memory indices, perform A/L operations on the plurality of packed data elements of the source packed data operand and the loaded plurality of data elements, and store a plurality of result data elements in the memory locations corresponding to the plurality of packed memory indices.Type: GrantFiled: September 27, 2013Date of Patent: January 24, 2017Assignee: Intel CorporationInventors: Igor Ermolaev, Bret L. Toll, Robert Valentine, Jesus Corbal San Adrian, Gautam B. Doshi, Rama Kishan V. Malladi, Prasenjit Chakraborty
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Patent number: 9450888Abstract: In one embodiment, the present invention includes a method for determining whether a packet received in an input/output (I/O) circuit of a node is destined for the node and if so, providing the packet to an egress queue of the I/O circuit and determining whether one or more packets are present in an ingress queue of the I/O circuit and if so, providing a selected packet to a first or second output register according to a global schedule that is independent of traffic flow. Other embodiments are described and claimed.Type: GrantFiled: October 25, 2013Date of Patent: September 20, 2016Assignee: Intel CorporationInventors: Michael Kauschke, Gautam B. Doshi
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Publication number: 20150095623Abstract: A processor including a decode unit to receive a vector indexed load plus arithmetic and/or logical (A/L) operation plus store instruction. The instruction is to indicate a source packed memory indices operand that is to have a plurality of packed memory indices. The instruction is also to indicate a source packed data operand that is to have a plurality of packed data elements. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to load a plurality of data elements from memory locations corresponding to the plurality of packed memory indices, perform A/L operations on the plurality of packed data elements of the source packed data operand and the loaded plurality of data elements, and store a plurality of result data elements in the memory locations corresponding to the plurality of packed memory indices.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Inventors: Igor Ermolaev, Bret L. Toll, Robert Valentine, Jesus Corbal San Adrian, Gautam B. Doshi, Rama Kishan V. Malladi, Prasenjit Chakraborty
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Publication number: 20140050224Abstract: In one embodiment, the present invention includes a method for determining whether a packet received in an input/output (I/O) circuit of a node is destined for the node and if so, providing the packet to an egress queue of the I/O circuit and determining whether one or more packets are present in an ingress queue of the I/O circuit and if so, providing a selected packet to a first or second output register according to a global schedule that is independent of traffic flow. Other embodiments are described and claimed.Type: ApplicationFiled: October 25, 2013Publication date: February 20, 2014Inventors: Michael Kauschke, Gautam B. Doshi
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Patent number: 8593960Abstract: In one embodiment, the present invention includes a method for determining whether a packet received in an input/output (I/O) circuit of a node is destined for the node and if so, providing the packet to an egress queue of the I/O circuit and determining whether one or more packets are present in an ingress queue of the I/O circuit and if so, providing a selected packet to a first or second output register according to a global schedule that is independent of traffic flow. Other embodiments are described and claimed.Type: GrantFiled: June 30, 2010Date of Patent: November 26, 2013Assignee: Intel CorporationInventors: Michael Kauschke, Gautam B. Doshi
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Patent number: 8578138Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.Type: GrantFiled: August 31, 2009Date of Patent: November 5, 2013Assignee: Intel CorporationInventors: Mahesh S. Natu, Thanunathan Rangarajan, Gautam B. Doshi, Shammanna M. Datta, Baskaran Ganesan, Mohan J. Kumar, Rajesh S. Parthasarathy, Frank Binns, Rajesh Nagaraja Murthy, Robert C. Swanson
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Publication number: 20120002675Abstract: In one embodiment, the present invention includes a method for determining whether a packet received in an input/output (I/O) circuit of a node is destined for the node and if so, providing the packet to an egress queue of the I/O circuit and determining whether one or more packets are present in an ingress queue of the I/O circuit and if so, providing a selected packet to a first or second output register according to a global schedule that is independent of traffic flow. Other embodiments are described and claimed.Type: ApplicationFiled: June 30, 2010Publication date: January 5, 2012Inventors: MICHAEL KAUSCHKE, Gautam B. Doshi
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Publication number: 20110055469Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.Type: ApplicationFiled: August 31, 2009Publication date: March 3, 2011Inventors: Mahesh S. Natu, Thanunathan Rangarajan, Gautam B. Doshi, Shammanna M. Datta, Baskaran Ganesan, Mohan J. Kumar, Rajesh S. Parthasarathy, Frank Binns, Rajesh Nagaraja Murthy, Robert C. Swanson
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Patent number: 7035891Abstract: A method and system are provided for performing soft error detection for integer addition and subtraction operations without the use of redundant logic. For integer addition and subtraction, compensate logic produces a compensate value utilizing arithmetic logic unit (ALU) result and operands. The compensate value is validated by the validate logic against a predetermined value to determine whether a soft error has occurred. Such compensate logic and validate logic operate on the integer operands and on the result produced by the ALU without redundant carry-propagate hardware.Type: GrantFiled: August 27, 2002Date of Patent: April 25, 2006Assignee: Intel CorporationInventors: Sivakumar Makineni, Gautam B. Doshi
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Patent number: 6820250Abstract: A method is provided for processing nested loops that include a modulo-scheduled inner loop within an outer loop. The nested loop is scheduled to execute the epilog stage of the inner loop for a given iteration of the outer loop with the prolog stage of the inner loop for the next iteration of the outer loop. For one embodiment of the invention, this is accomplished by initializing an epilog counter for the inner loop to a value that bypasses draining the software pipeline. This causes the processor to exit the inner loop before it begins draining the inner loop pipeline. The inner loop pipeline is drained during the next iteration of the outer loop, while the inner loop pipeline fills for the next iteration of the outer loop.Type: GrantFiled: May 9, 2002Date of Patent: November 16, 2004Assignee: Intel CorporationInventors: Kalyan Muthukumar, Gautam B. Doshi
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Publication number: 20040123280Abstract: An embodiment of a compiler technique for decreasing sparse matrix computation runtime parallelizes loads from adjacent iterations of unrolled loop code. A dependence check code is statically inserted to identify dependence between store and load dynamically, and information is passed to a code scheduler for scheduling independent parallel computation and potentially dependent computations at suitable latencies.Type: ApplicationFiled: December 19, 2002Publication date: June 24, 2004Inventors: Gautam B. Doshi, Dattatraya Kulkarni, Anthony J. Roide, Antonio C. Valles
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Publication number: 20040044717Abstract: A method and system are provided for performing soft error detection for integer addition and subtraction operations without the use of redundant logic. For integer addition and subtraction, compensate logic produces a compensate value utilizing arithmetic logic unit (ALU) result and operands. The compensate value is validated by the validate logic against a predetermined value to determine whether a soft error has occurred. Such compensate logic and validate logic operate on the integer operands and on the result produced by the ALU without redundant carry-propagate hardware.Type: ApplicationFiled: August 27, 2002Publication date: March 4, 2004Inventors: Sivakumar Makineni, Gautam B. Doshi
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Publication number: 20040015934Abstract: A method is provided for processing nested loops that include a modulo-scheduled inner loop within an outer loop. The nested loop is scheduled to execute the epilog stage of the inner loop for a given iteration of the outer loop with the prolog stage of the inner loop for the next iteration of the outer loop. For one embodiment of the invention, this is accomplished by initializing an epilog counter for the inner loop to a value that bypasses draining the software pipeline. This causes the processor to exit the inner loop before it begins draining the inner loop pipeline. The inner loop pipeline is drained during the next iteration of the outer loop, while the inner loop pipeline fills for the next iteration of the outer loop.Type: ApplicationFiled: May 9, 2002Publication date: January 22, 2004Inventors: Kalyan Muthukumar, Gautam B. Doshi
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Patent number: 6578059Abstract: A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.Type: GrantFiled: October 10, 1998Date of Patent: June 10, 2003Assignee: Institute for the Development of Emerging Architectures, L.L.C.Inventors: Jerome C. Huck, Peter Markstein, Glenn T. Colon-Bonet, Alan H. Karp, Roger Golliver, Michael Morrison, Gautam B. Doshi
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Patent number: 6370639Abstract: A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.Type: GrantFiled: October 10, 1998Date of Patent: April 9, 2002Assignee: Institute for the Development of Emerging Architectures L.L.C.Inventors: Jerome C. Huck, Peter Markstein, Glenn T. Colon-Bonet, Alan H. Karp, Roger Golliver, Michael Morrison, Gautam B. Doshi, Guillermo Juan Rozas
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Patent number: 6321330Abstract: The present invention provides a mechanism for prefetching array data efficiently from within a loop. A prefetch instruction is parameterized by a register from a set of rotating registers. On each loop iteration, a prefetch is implemented according to the parameterized prefetch instruction, and the address targeted by the prefetch instruction is adjusted. The registers are rotated for each loop iteration, and the prefetch instruction parameterized by the rotating register is adjusted accordingly. The number of iterations between prefetches for a given array is determined by the number of elements in the set of rotating register.Type: GrantFiled: May 28, 1999Date of Patent: November 20, 2001Assignee: Intel CorporationInventors: Gautam B. Doshi, Kalyan Muthukumar
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Patent number: 6321327Abstract: A method is provided for loading a packed floating-point operand into a register file entry having one or more associated implicit bits. The packed floating point operand includes multiple component operands. Significand and exponent bits for each component operand are copied to corresponding fields of the register entry, and the exponent bits are tested to determine whether the component operand is normalized. An implicit bit corresponding to the component operand is set when the component operand is normalized.Type: GrantFiled: December 30, 1998Date of Patent: November 20, 2001Assignee: Intel CorporationInventors: Sivakumar Makineni, Sunnhyuk Kimn, Gautam B. Doshi, Roger A. Golliver
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Patent number: 6301705Abstract: The present invention is generally directed to a system and method for supporting speculative execution of an instruction set for a central processing unit (CPU) including non-speculative and speculative instructions. In accordance with one aspect of the invention a method includes the steps of evaluating the instructions of the program to determine whether the individual instructions are speculative or non-speculative, and assessing each of the speculative instructions to determine whether it generates an exception. For each of the speculative instructions that generates an exception, the method then encode a deferred exception token (DET) into an unused register value of a register of the CPU. In accordance with another aspect of the invention, a system is provided, which system includes circuitry configured to evaluate the instructions of the instruction set to determine whether the individual instructions are speculative or non-speculative.Type: GrantFiled: October 1, 1998Date of Patent: October 9, 2001Assignee: Institute for the Development of Emerging Architectures, L.L.C.Inventors: Gautam B. Doshi, Peter Markstein, Alan H. Karp, Jerome C. Huck, Glenn T. Colon-Bonet, Michael Morrison
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Patent number: 6292886Abstract: A system for processing SIMD operands in a packed data format includes a scalar FMAC and a vector FMAC coupled to a register file through an operand delivery module. For vector operations, the operand delivery module bit steers a SIMD operand of the packed operand into an unpacked operand for processing by the first execution unit. Another SIMD operand is processed by the vector execution unit.Type: GrantFiled: October 12, 1998Date of Patent: September 18, 2001Assignee: Intel CorporationInventors: Sivakumar Makineni, Sunnhyuk Kimn, Gautam B. Doshi, Roger A. Golliver
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Patent number: 6212539Abstract: A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.Type: GrantFiled: October 10, 1998Date of Patent: April 3, 2001Assignee: Institute for the Development of Emerging Architectures, L.L.C.Inventors: Jerome C. Huck, Peter Markstein, Glenn T. Colon-Bonet, Alan H. Karp, Roger Golliver, Michael Morrison, Gautam B. Doshi