Patents by Inventor Gautam CHAKRABARTI

Gautam CHAKRABARTI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9747107
    Abstract: A system and method for compiling or runtime executing a fork-join data parallel program with function calls. In one embodiment, the system includes: (1) a partitioner operable to partition groups into a master group and at least one worker group and (2) a thread designator associated with the partitioner and operable to designate only one thread from the master group for execution and all threads in the at least one worker group for execution.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: August 29, 2017
    Assignee: Nvidia Corporation
    Inventors: Yuan Lin, Gautam Chakrabarti, Jaydeep Marathe, Okwan Kwon, Amit Sabne
  • Patent number: 9727338
    Abstract: A system and method of translating functions of a program. In one embodiment, the system includes: (1) a local-scope variable identifier operable to identify local-scope variables employed in the at least some of the functions as being either thread-shared local-scope variables or thread-private local-scope variables and (2) a function translator associated with the local-scope variable identifier and operable to translate the at least some of the functions to cause thread-shared memory to be employed to store the thread-shared local-scope variables and thread-private memory to be employed to store the thread-private local-scope variables.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: August 8, 2017
    Assignee: Nvidia Corporation
    Inventors: Yuan Lin, Gautam Chakrabarti, Jaydeep Marathe, Okwan Kwon, Amit Sabne
  • Patent number: 9710275
    Abstract: A system and method for allocating shared memory of differing properties to shared data objects and a hybrid stack data structure. In one embodiment, the system includes: (1) a hybrid stack creator configured to create, in the shared memory, a hybrid stack data structure having a lower portion having a more favorable property and a higher portion having a less favorable property and (2) a data object allocator associated with the hybrid stack creator and configured to allocate storage for shared data object in the lower portion if the lower portion has a sufficient remaining capacity to contain the shared data object and alternatively allocate storage for the shared data object in the higher portion if the lower portion has an insufficient remaining capacity to contain the shared data object.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: July 18, 2017
    Assignee: Nvidia Corporation
    Inventors: Jaydeep Marathe, Yuan Lin, Gautam Chakrabarti, Okwan Kwon, Amit Sabne
  • Patent number: 9436475
    Abstract: A system and method for executing sequential code in the context of a single-instruction, multiple-thread (SIMT) processor. In one embodiment, the system includes: (1) a pipeline control unit operable to create a group of counterpart threads of the sequential code, one of the counterpart threads being a master thread, remaining ones of the counterpart threads being slave threads and (2) lanes operable to: (2a) execute certain instructions of the sequential code only in the master thread, corresponding instructions in the slave threads being predicated upon the certain instructions and (2b) broadcast branch conditions in the master thread to the slave threads.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: September 6, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Gautam Chakrabarti, Yuan Lin, Jaydeep Marathe, Okwan Kwon, Amit Sabne
  • Patent number: 9292265
    Abstract: Basic blocks within a thread program are characterized for convergence based on variance analysis or corresponding instructions. Each basic block is marked as divergent based on transitive control dependence on a block that is either divergent or comprising a variant branch condition. Convergent basic blocks that are defined by invariant instructions are advantageously identified as candidates for scalarization by a thread program compiler.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: March 22, 2016
    Assignee: NVIDIA Corporation
    Inventors: Vinod Grover, Yunsup Lee, Xiangyun Kong, Gautam Chakrabarti, Ronny M. Krashinsky
  • Publication number: 20140130052
    Abstract: A system and method for compiling or runtime executing a fork-join data parallel program with function calls. In one embodiment, the system includes: (1) a partitioner operable to partition groups into a master group and at least one worker group and (2) a thread designator associated with the partitioner and operable to designate only one thread from the master group for execution and all threads in the at least one worker group for execution.
    Type: Application
    Filed: December 21, 2012
    Publication date: May 8, 2014
    Applicant: Nvidia Corporation
    Inventors: Yuan Lin, Gautam Chakrabarti, Jaydeep Marathe, Okwan Kwon, Amit Sabne
  • Publication number: 20140129812
    Abstract: A system and method for executing sequential code in the context of a single-instruction, multiple-thread (SIMT) processor. In one embodiment, the system includes: (1) a pipeline control unit operable to create a group of counterpart threads of the sequential code, one of the counterpart threads being a master thread, remaining ones of the counterpart threads being slave threads and (2) lanes operable to: (2a) execute certain instructions of the sequential code only in the master thread, corresponding instructions in the slave threads being predicated upon the certain instructions and (2b) broadcast branch conditions in the master thread to the slave threads.
    Type: Application
    Filed: December 21, 2012
    Publication date: May 8, 2014
    Applicant: Nvidia Corporation
    Inventors: Gautam Chakrabarti, Yuan Lin, Jaydeep Marathe, Okwan Kwon, Amit Sabne
  • Publication number: 20140129783
    Abstract: A system and method for allocating shared memory of differing properties to shared data objects and a hybrid stack data structure. In one embodiment, the system includes: (1) a hybrid stack creator configured to create, in the shared memory, a hybrid stack data structure having a lower portion having a more favorable property and a higher portion having a less favorable property and (2) a data object allocator associated with the hybrid stack creator and configured to allocate storage for shared data object in the lower portion if the lower portion has a sufficient remaining capacity to contain the shared data object and alternatively allocate storage for the shared data object in the higher portion if the lower portion has an insufficient remaining capacity to contain the shared data object.
    Type: Application
    Filed: December 21, 2012
    Publication date: May 8, 2014
    Applicant: NVIDIA
    Inventors: Jaydeep Marathe, Gautam Chakrabarti, Yuan Lin, Okwan Kwon, Amit Sabne
  • Publication number: 20140130021
    Abstract: A system and method of translating functions of a program. In one embodiment, the system includes: (1) a local-scope variable identifier operable to identify local-scope variables employed in the at least some of the functions as being either thread-shared local-scope variables or thread-private local-scope variables and (2) a function translator associated with the local-scope variable identifier and operable to translate the at least some of the functions to cause thread-shared memory to be employed to store the thread-shared local-scope variables and thread-private memory to be employed to store the thread-private local-scope variables.
    Type: Application
    Filed: December 21, 2012
    Publication date: May 8, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Yuan Lin, Gautam Chakrabarti, Jaydeep Marathe, Okwan Kwon, Amit Sabne
  • Publication number: 20130305021
    Abstract: Basic blocks within a thread program are characterized for convergence based on variance analysis or corresponding instructions. Each basic block is marked as divergent based on transitive control dependence on a block that is either divergent or comprising a variant branch condition. Convergent basic blocks that are defined by invariant instructions are advantageously identified as candidates for scalarization by a thread program compiler.
    Type: Application
    Filed: May 9, 2012
    Publication date: November 14, 2013
    Inventors: Vinod GROVER, Yunsup LEE, Xiangyun KONG, Gautam CHAKRABARTI, Ronny M. KRASHINSKY