Abstract: Systems and methods are described for controlling or monitoring a wide variety of target hardware, which may use various interfaces and protocols, via non-customized software, without requiring additional software to interface between the non-customized software and the target hardware. An application repository can include a variety of software applications available to end users. An end user may request one or more such applications, and specify target hardware controlled or monitored by the applications. The app repository can then generate a hardware configuration template, corresponding to a configuration of a field-programmable hardware layer on a bridge device of the end user, which routes data between inputs and outputs of the target hardware and a memory on the bridge device. The template and applications can then be provisioned on the bridge device, such that the applications can execute to control and monitor the target hardware via interaction with the memory.

Abstract: A highly efficient method for scheduling operations to be performed by a fine grained graph processor is performed by a fine gained graph processor based system. The method first determines a set of execution paths for executing a sequence of operations. Each path logically passes through a set of execution units of the fine grained graph processor. The execution units are interconnected by BSEs and RSEs, each of which includes one or more memory elements. The method also determines availability of each execution path within the set by determining availability of execution units of the path. The checking of availability of execution units checks from one execution unit to another in the same row first, one execution unit to another in different rows on the same plane secondly and then one execution unit to another in different planes. The method is designed to reduce execution cost.

Abstract: A novel scheduler design is provided that schedules a set of operations to an array of similar or dissimilar, candidate operations on a cycle by cycle basis, out of a total number of operations. The array of similar or dissimilar units can be atomic in nature or ALU like or complete processors. The scheduler is able to map the operations in a data flow/sequencing graph to the two dimensional or 3 dimensional array (which can be extended to a multi-dimensional array) optimally so as to minimize the total execution times. The mapping is path based computation, where a particular sequence of instructions is routed through the underlying matrix in path that minimized the number of memory hops.

Abstract: A graph processor has a planar matrix array of system resources. Resources in a same matrix or different planar matrices are interconnected through port blocks or global switched memories. Each port block includes a broadcast switch element and a receive switch element. The graph processor executes atomic execution paths that are generated from data flow graphs or computer programs by a scheduler. The scheduler linearizes resources and memories. The scheduler further maintains a linearized score board for tracking states of the resources.

Abstract: An intelligent routing and switching system includes an interface for coupling said system to an external network and a switch fabric for selectively routing bits of data being exchanged with an external network through the interface. The switch fabric includes an array of multiport switching elements each including switches and memory elements for introducing programmable delays in selected ones of the bits being routed. The routing and switching system further includes a first controller for implementing a routing table and scheduler in accordance with a sequencing graph to route bits of data through the switch fabric and a second controller for generating the sequencing graph and for allocating input and output slots for inputting and outputting data through the interface.

Abstract: A physically non-distributed microprocessor-based computer includes a microprocessor, and a random access memory device, a mass storage device, and an input-output port device, all operable from the microprocessor and including an interface for receiving and transmitting data in packet form. A novel packet-based data channel extends between the microprocessor and the interfaces of the devices to provide communication between the microprocessor and the devices. By varying the size of the packets in accordance with actual data transmission requirements improved computer performance is achieved.