Abstract: A circuit includes a digital-to-analog converter and a gain stage. The gain stage includes: an operational amplifier; a variable gain network; and a leakage current control circuit. A first input of the operational amplifier is coupled to an input of the gain stage. An output of the operational amplifier is coupled to an output of the gain stage. A first terminal of the variable gain network is coupled to the second input of the operational amplifier. A second terminal of the variable gain network is coupled to the output of the operational amplifier. A first terminal of the leakage current control circuit is coupled to the output of the operational amplifier. A second terminal of the leakage current control circuit coupled to a third terminal of the variable gain network.

Abstract: The techniques and circuits, described herein, include solutions for reducing measure current settling time in source measurement units (SMUs) during a force voltage mode of operation. An SMU includes a force amplifier having a first voltage input, a second voltage input, a feedback voltage input, and a output. A resistor has a first terminal coupled to the output of the force amplifier, and a second terminal. A switch is coupled between the second terminal of the resistor and the feedback voltage input of the force amplifier. The switch is closed in the force voltage mode, creating a feedback path which the resistor is contained within. A series combination of a capacitor and a resistor is coupled to a gate of a transistor within the force amplifier, which results in improved measure current settling time compared to alternative techniques.

Abstract: The techniques and circuits, described herein, include solutions for error compensation in source measurement units (SMUs). An example SMU is capable of both sourcing current to a device under test (DUT) and measuring current through the DUT. An SMU may include a sensing resistor coupled in series with the DUT. A voltage across the sensing resistor may be measured by a current sensing amplifier in order to determine the output current through the DUT. In practice, the resistance of the sensing resistor may vary depending on manufacturing tolerances, etc. A gain of the current sensing amplifier may be calibrated in order to compensate for sensing resistor variance, which increases the accuracy with which current to the DUT can be sourced and measured.

Abstract: A circuit includes a digital-to-analog converter and a gain stage. The gain stage includes: an operational amplifier; a variable gain network; and a leakage current control circuit. A first input of the operational amplifier is coupled to an input of the gain stage. An output of the operational amplifier is coupled to an output of the gain stage. A first terminal of the variable gain network is coupled to the second input of the operational amplifier. A second terminal of the variable gain network is coupled to the output of the operational amplifier. A first terminal of the leakage current control circuit is coupled to the output of the operational amplifier. A second terminal of the leakage current control circuit coupled to a third terminal of the variable gain network.

Abstract: According to an aspect of the present invention, different reference voltage levels are used for different stages of a multi-stage analog to digital converter (ADC). In one embodiment, the amplification and unity gain bandwidth (UGB) requirements in the first stage is reduced as a result.

Abstract: Low voltage transistors are used in high voltage environment. The low voltage transistors may be used in the path of processing of a signal to increase the throughput performance. By using high voltage supply associated with the high voltage environment, a higher SNR may be attained. Various techniques are implemented to ensure that the low voltage transistors are not damaged by prolonged exposure to high voltages.

Abstract: A clamping circuit containing a transistor and a current amplifier. The transistor is designed to turn on when the voltage at a node exceeds (falls below) a specified upper (lower) level. The current amplifier is designed to draw substantial amount of current when the transistor is turned on to clamp the voltage at the node to the desired level.

Abstract: An aspect of the present invention reduces droop in the reference signal provided to ADCs. A compensation resistor of appropriate resistance value is provided in the path of the reference signal to minimize the droop.