Patents by Inventor Gautam Salil Nandi

Gautam Salil Nandi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240319260
    Abstract: In described examples, a test control circuit includes a subsystem and a transition control circuit. The subsystem outputs test signals to, and receives and measures response signals of, a device under test (DUT). The transition control circuit operates the test control circuit in response to a first operational state information indicating a first mode and a first set of configuration settings; receives a Transition Trigger signal and a second operational state information indicating a second mode and a second set of configuration settings; and, by performing allowed mode changes and in response to receiving the Transition Trigger signal, transitions the test control circuit to operating in response to the second operational state information. Allowed mode changes are restricted to: from a DUT driving mode to a DUT non-driving mode, from a DUT non-driving mode to another DUT non-driving mode, or from a DUT non-driving mode to a DUT driving mode.
    Type: Application
    Filed: September 29, 2023
    Publication date: September 26, 2024
    Inventors: Tanmay Neema, Rajavelu Thinakaran, Gautam Salil Nandi, Vishal Monteiro, Deepak Kumar Meher
  • Publication number: 20240310411
    Abstract: An apparatus includes a circuit including a force amplifier having an output, a resistor having a first terminal coupled to the output of the force amplifier, and a second terminal. The circuit also includes a diode clamp including a first diode having a first terminal coupled to the first terminal of the resistor, and having a second terminal coupled to the second terminal of the resistor, the first diode having a first orientation. The diode clamp also includes a second diode coupled in parallel with the first diode between the first and second terminals of the resistor, the second diode having a second orientation opposite than the first diode.
    Type: Application
    Filed: March 14, 2024
    Publication date: September 19, 2024
    Inventors: Rajavelu Thinakaran, Gautam Salil Nandi, Hariharan Srinivasan, Rahul Shaw, Abhishek Ghosh, Taras Dudar
  • Publication number: 20240310432
    Abstract: In some examples, a method of performing measurement of a device under test (DUT) coupled to a connector includes determining a first voltage signal representative of a current of the DUT, the current flowing through the connector. The method also includes determining a second voltage signal representative of a voltage of the DUT, as provided at the connector. The method also includes determining a calibration current according to the first voltage signal. The method also includes modifying measurement of the DUT according to the calibration current.
    Type: Application
    Filed: June 29, 2023
    Publication date: September 19, 2024
    Inventors: Gautam Salil NANDI, Rajavelu THINAKARAN, Hariharan SRINIVASAN
  • Patent number: 12028085
    Abstract: In described examples, a digital-to-analog converter includes an output, multiple most significant bit (MSB) connector resistors each having a resistance R??R, multiple least significant bit (LSB) connector resistors each having a resistance R, and multiple binary arm resistors each having a resistance 2R. The MSB connector resistors are coupled in a series beginning with the output and ending with a first one of the LSB connector resistors, and the LSB connector resistors are coupled in a series beginning with the first LSB connector resistor. A terminal of one of the binary arm resistors is coupled to an ending of the LSB connector resistor series, and a terminal of each of different remaining ones of the binary arm resistors is coupled between a different pair of the MSB and/or LSB connector resistors.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: July 2, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tanmay Neema, Gautam Salil Nandi, Rishubh Khurana, Atul Kumar Agrawal, Deepak Kumar Meher
  • Patent number: 11936395
    Abstract: In described examples, a digital-to-analog converter (DAC) includes an output, a ground, a reference voltage terminal, an input code terminal, multiple switches, multiple resistors, and a controller. The switches couple to the reference voltage terminal when activated and to the ground when deactivated. The resistors are variously coupled between corresponding ones of the switches and the output, so that activating the switches causes the DAC to output an output voltage. The controller is coupled to the input code terminal and coupled to control the switches. The controller generates an output code based on an input code in response to at least one differential nonlinearity error greater than one least significant bit voltage. The input code corresponds to a first ideal output voltage, the output code corresponds to a second, different ideal output voltage. The controller generates an output voltage by controlling the switches using the output code.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: March 19, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tanmay Neema, Gautam Salil Nandi, Rishubh Khurana, Atul Kumar Agrawal, Deepak Kumar Meher
  • Publication number: 20230238972
    Abstract: In described examples, a digital-to-analog converter includes an output, multiple most significant bit (MSB) connector resistors each having a resistance R??R, multiple least significant bit (LSB) connector resistors each having a resistance R, and multiple binary arm resistors each having a resistance 2R. The MSB connector resistors are coupled in a series beginning with the output and ending with a first one of the LSB connector resistors, and the LSB connector resistors are coupled in a series beginning with the first LSB connector resistor. A terminal of one of the binary arm resistors is coupled to an ending of the LSB connector resistor series, and a terminal of each of different remaining ones of the binary arm resistors is coupled between a different pair of the MSB and/or LSB connector resistors.
    Type: Application
    Filed: January 27, 2022
    Publication date: July 27, 2023
    Inventors: Tanmay Neema, Gautam Salil Nandi, Rishubh Khurana, Atul Kumar Agrawal, Deepak Kumar Meher
  • Publication number: 20230238973
    Abstract: In described examples, a digital-to-analog converter (DAC) includes an output, a ground, a reference voltage terminal, an input code terminal, multiple switches, multiple resistors, and a controller. The switches couple to the reference voltage terminal when activated and to the ground when deactivated. The resistors are variously coupled between corresponding ones of the switches and the output, so that activating the switches causes the DAC to output an output voltage. The controller is coupled to the input code terminal and coupled to control the switches. The controller generates an output code based on an input code in response to at least one differential nonlinearity error greater than one least significant bit voltage. The input code corresponds to a first ideal output voltage, the output code corresponds to a second, different ideal output voltage. The controller generates an output voltage by controlling the switches using the output code.
    Type: Application
    Filed: January 27, 2022
    Publication date: July 27, 2023
    Inventors: Tanmay Neema, Gautam Salil Nandi, Rishubh Khurana, Atul Kumar Agrawal, Deepak Kumar Meher
  • Patent number: 10948933
    Abstract: A digital-to-analog converter includes a resistor ladder, a first switch and a protection circuit. The first switch includes a first terminal and a second terminal that are respectively coupled to a rung of the resistor ladder and a reference voltage node. The protection circuit is coupled to the reference voltage node and to a reference voltage input terminal. The protection circuit includes a second switch, a third switch, and a fourth switch. First and second terminals of the second switch are respectively coupled to the reference voltage node and the reference voltage input terminal. First and second terminals of the third switch are respectively coupled to the reference voltage node and a reference voltage feedback terminal. The first and second terminals of the fourth switch are respectively coupled to the reference voltage input terminal and the reference voltage feedback terminal.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: March 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gautam Salil Nandi, Mit Bhattacharya
  • Patent number: 10862493
    Abstract: An integrated circuit includes a digital-to-analog converter (DAC) core including a plurality of thermometric arms and an R-2R ladder, the DAC core to convert a DAC code to an analog signal. The integrated circuit includes additional components as well. A differential non-linearity (DNL) calibration circuit outputs DNL coefficients based on the DAC code. A memory stores a value indicative of a product of a resistor temperature coefficient (TC) and a resistor self-heating coefficient (SHC). A current DAC (IDAC) couples to the R-2R ladder. A self-heating calibration circuit generates a self-heating trim code based on the value from the memory. An adder adds a value indicative of the DNL coefficients with the self-heating trim code to generate an IDAC trim code and provides the IDAC trim code to the IDAC to trim the R-2R ladder.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: December 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Atul Kumar Agrawal, Gautam Salil Nandi, Siddharth Malhotra, Tanmay Neema
  • Publication number: 20200333814
    Abstract: A digital-to-analog converter includes a resistor ladder, a first switch and a protection circuit. The first switch includes a first terminal and a second terminal that are respectively coupled to a rung of the resistor ladder and a reference voltage node. The protection circuit is coupled to the reference voltage node and to a reference voltage input terminal. The protection circuit includes a second switch, a third switch, and a fourth switch. First and second terminals of the second switch are respectively coupled to the reference voltage node and the reference voltage input terminal. First and second terminals of the third switch are respectively coupled to the reference voltage node and a reference voltage feedback terminal. The first and second terminals of the fourth switch are respectively coupled to the reference voltage input terminal and the reference voltage feedback terminal.
    Type: Application
    Filed: April 17, 2019
    Publication date: October 22, 2020
    Inventors: Gautam Salil NANDI, Mit BHATTACHARYA
  • Publication number: 20200252073
    Abstract: An integrated circuit includes a digital-to-analog converter (DAC) core including a plurality of thermometric arms and an R-2R ladder, the DAC core to convert a DAC code to an analog signal. The integrated circuit includes additional components as well. A differential non-linearity (DNL) calibration circuit outputs DNL coefficients based on the DAC code. A memory stores a value indicative of a product of a resistor temperature coefficient (TC) and a resistor self-heating coefficient (SHC). A current DAC (IDAC) couples to the R-2R ladder. A self-heating calibration circuit generates a self-heating trim code based on the value from the memory. An adder adds a value indicative of the DNL coefficients with the self-heating trim code to generate an IDAC trim code and provides the IDAC trim code to the IDAC to trim the R-2R ladder.
    Type: Application
    Filed: April 21, 2020
    Publication date: August 6, 2020
    Inventors: Atul Kumar AGRAWAL, Gautam Salil NANDI, Siddharth MALHOTRA, Tanmay NEEMA
  • Patent number: 10673450
    Abstract: An integrated circuit includes a digital-to-analog converter (DAC) core including a plurality of thermometric arms and an R-2R ladder, the DAC core to convert a DAC code to an analog signal. The integrated circuit includes additional components as well. A differential non-linearity (DNL) calibration circuit outputs DNL coefficients based on the DAC code. A memory stores a value indicative of a product of a resistor temperature coefficient (TC) and a resistor self-heating coefficient (SHC). A current DAC (IDAC) couples to the R-2R ladder. A self-heating calibration circuit generates a self-heating trim code based on the value from the memory. An adder adds a value indicative of the DNL coefficients with the self-heating trim code to generate an IDAC trim code and provides the IDAC trim code to the IDAC to trim the R-2R ladder.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: June 2, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Atul Kumar Agrawal, Gautam Salil Nandi, Siddharth Malhotra, Tanmay Neema
  • Publication number: 20200162090
    Abstract: An integrated circuit includes a digital-to-analog converter (DAC) core including a plurality of thermometric arms and an R-2R ladder, the DAC core to convert a DAC code to an analog signal. The integrated circuit includes additional components as well. A differential non-linearity (DNL) calibration circuit outputs DNL coefficients based on the DAC code. A memory stores a value indicative of a product of a resistor temperature coefficient (TC) and a resistor self-heating coefficient (SHC). A current DAC (IDAC) couples to the R-2R ladder. A self-heating calibration circuit generates a self-heating trim code based on the value from the memory. An adder adds a value indicative of the DNL coefficients with the self-heating trim code to generate an IDAC trim code and provides the IDAC trim code to the IDAC to trim the R-2R ladder.
    Type: Application
    Filed: November 20, 2018
    Publication date: May 21, 2020
    Inventors: Atul Kumar AGRAWAL, Gautam Salil NANDI, Siddharth MALHOTRA, Tanmay NEEMA
  • Patent number: 10340941
    Abstract: A digital-to-analog converter (DAC) includes a first stage comprising a plurality of first circuit arms coupled together, each first circuit arm including a resistor. A second stage includes a plurality of second circuit arms coupled together, each second circuit arm comprising a first resistor and a pair of series-connected resistors. The first resistors of the second circuit arms are connected in series. A current digital-to-analog converter (IDAC) trim circuit is connected to a plurality, but not all, of the second circuit arms of the second stage. The IDAC trim circuit includes a plurality of first current sources. Each first current source is coupled to a respective node between a pair of the series-connected resistors of a corresponding second circuit arm, and each of the first current sources is configured to produce a same current level as the other first current sources.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: July 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Gautam Salil Nandi
  • Patent number: 9705524
    Abstract: One example includes an R2R digital-to-analog converter (DAC) circuit. The circuit includes at least one scaling circuit configured to apply a scale-factor with respect to a nominal voltage range defined by a low-voltage rail and a reference voltage to define a scaled voltage range. The scale-factor can be positive and less than one. The circuit also includes an R2R ladder circuit configured to generate an analog ladder voltage corresponding to a digital input signal. The analog ladder voltage can have an amplitude in the scaled voltage range. The circuit further includes an output stage configured to apply an inverse of the scale-factor to the analog ladder voltage to generate an output voltage.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: July 11, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gautam Salil Nandi, Sundarasiva Rao Giduturi
  • Publication number: 20170126244
    Abstract: One example includes an R2R digital-to-analog converter (DAC) circuit. The circuit includes at least one scaling circuit configured to apply a scale-factor with respect to a nominal voltage range defined by a low-voltage rail and a reference voltage to define a scaled voltage range. The scale-factor can be positive and less than one. The circuit also includes an R2R ladder circuit configured to generate an analog ladder voltage corresponding to a digital input signal. The analog ladder voltage can have an amplitude in the scaled voltage range. The circuit further includes an output stage configured to apply an inverse of the scale-factor to the analog ladder voltage to generate an output voltage.
    Type: Application
    Filed: October 28, 2016
    Publication date: May 4, 2017
    Inventors: GAUTAM SALIL NANDI, SUNDARASIVA RAO GIDUTURI
  • Patent number: 7259609
    Abstract: A clamping circuit containing a transistor and a current amplifier. The transistor is designed to turn on when the voltage at a node exceeds (falls below) a specified upper (lower) level. The current amplifier is designed to draw substantial amount of current when the transistor is turned on to clamp the voltage at the node to the desired level.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: August 21, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Visvesvaraya A. Pentakota, Vineet Mishra, Shakti Shankar Rath, Gautam Salil Nandi
  • Patent number: 7161521
    Abstract: According to an aspect of the present invention, different reference voltage levels are used for different stages of a multi-stage analog to digital converter (ADC). In one embodiment, the amplification and unity gain bandwidth (UGB) requirements in the first stage is reduced as a result.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: January 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Gautam Salil Nandi, Visvesvaraya A. Pentakota, Nitin Agarwal, Sandeep Kesrimal Oswal
  • Patent number: 7088149
    Abstract: Low voltage transistors are used in high voltage environment. The low voltage transistors may be used in the path of processing of a signal to increase the throughput performance. By using high voltage supply associated with the high voltage environment, a higher SNR may be attained. Various techniques are implemented to ensure that the low voltage transistors are not damaged by prolonged exposure to high voltages.
    Type: Grant
    Filed: November 29, 2003
    Date of Patent: August 8, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Anand Hariraj Udupa, Visvesvaraya A. Pentakota, Shakti Shankar Rath, Gautam Salil Nandi, Vineet Mishra, Ravishankar S. Ayyagari, Nitin Agarwal
  • Patent number: 6906658
    Abstract: An aspect of the present invention reduces droop in the reference signal provided to ADCs. A compensation resistor of appropriate resistance value is provided in the path of the reference signal to minimize the droop.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: June 14, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Visvesvaraya A. Pentakota, Gautam Salil Nandi