Abstract: Described are techniques for interleaving range and Doppler radar processing. A data cube is memory accessed differently, from one look period to the next, which allows Doppler processing for a current look period to happen in parallel with range processing for a next look period. Range processing for a first look period writes to rows of the data cube; Doppler processing reads from and empties its columns. But before Doppler processing can finish, a second look period begins. Rather than re-writing to the rows, range processing in the second look period writes to the columns just emptied by the ongoing Doppler processing. Doppler processing for the first look period is allowed to finish by executing during processing idle times in the second period, e.g., in-between chirps. With better processor utilization, Doppler processing is afforded more time to do its complex operations, while keeping look periods as short as possible.

Abstract: A restraint bracket of a bracket assembly mounted to a lower surface of a support frame of a person support apparatus is disclosed. The restraint bracket includes a bracket body having an upper surface and a lower surface opposite the upper surface, a pair of flanges formed on the upper surface of the bracket body, and an attachment member extending from the lower surface of the bracket body, the attachment member having a first end and a second end opposite the first end, the first end and the second end fixed to the lower surface of the bracket body.

Abstract: A controller of a boost converter may be configured to dynamically adjust conditions within the boost converter by monitoring conditions in the boost converter. For example, the controller may determine an current inductance value for an inductor of the boost converter by monitoring a current through the inductor. When the inductance value of the inductor is known, a slope compensation value may be used in determining a transition time between charging the inductor of the boost converter and discharging the inductor.

Abstract: Audio amplification may be improved by controlling an audio amplifier based on the audio signal being amplified. For example, when the audio signal level increases or decreases, a boost voltage provided to an audio amplifier by a boost converter may also be increased or decreased. In another example, when the audio signal level decrease below a certain level, the audio amplifier may be switched from amplifying the audio signal with a boost converter input to amplifying the audio signal with a low voltage input. Control of the audio amplifier may be implemented in a digital boost converter controller coupled to the boost converter and/or the audio amplifier.

Abstract: Audio amplification may be improved by controlling an audio amplifier based on the audio signal being amplified. For example, when the audio signal level increases or decreases, a boost voltage provided to an audio amplifier by a boost converter may also be increased or decreased. In another example, when the audio signal level decrease below a certain level, the audio amplifier may be switched from amplifying the audio signal with a boost converter input to amplifying the audio signal with a low voltage input. Control of the audio amplifier may be implemented in a digital boost converter controller coupled to the boost converter and/or the audio amplifier.

Abstract: A controller of a boost converter may be configured to dynamically adjust conditions within the boost converter by monitoring conditions in the boost converter. For example, the controller may determine an current inductance value for an inductor of the boost converter by monitoring a current through the inductor. When the inductance value of the inductor is known, a slope compensation value may be used in determining a transition time between charging the inductor of the boost converter and discharging the inductor.

Abstract: Because of the natural ability to reject clock jitter, the SRC circuits include an internal oscillator to provide an operating clock signal. The internal oscillator can be operated independently of any external frequency control signal, including input and output frame clocks. The internal oscillator can be implemented as a relatively low-cost fixed frequency oscillator. The use of a relatively low precision, inexpensive internal oscillator in an SRC circuit reduces the overall cost of SRC circuits while providing acceptable performance. Accordingly, reducing costs of SRC circuits also has a positive cost/benefit affect on the digital signal processing systems that use SRC circuits.

Abstract: An integrated circuit and method for indicating the integrated circuit to enter into a scan mode are disclosed. A designated signal, such as an analog supply signal, for an analog block of an integrated circuit is utilized for indicating entry of a digital block of the integrated circuit into a scan mode. Operations of the analog block and the digital block are generally independent from each other during scan mode. Prior to the digital block utilizing the designated signal, voltage rails for the designated signal are resolved with the voltage rails of a digital supply signal for the digital block.

Abstract: An integrated circuit and method for indicating the integrated circuit to enter into a scan mode are disclosed. A designated signal, such as an analog supply signal, for an analog block of an integrated circuit is utilized for indicating entry of a digital block of the integrated circuit into a scan mode. Operations of the analog block and the digital block are generally independent from each other during scan mode. Prior to the digital block utilizing the designated signal, voltage rails for the designated signal are resolved with the voltage rails of a digital supply signal for the digital block.

Abstract: An asynchronous sample rate converter for converting a first sample rate in a signal to a second sample rate in the same signal is presented. The signal is first provided as input to an interpolator which upsamples the signal to form a signal having sample rate UFs1 where the upsampling factor U is a variable that is directly related to the ratio Fs2/Fs1. The resampler then linearly interpolates the upsampled signal to form a signal having sample rate DFs2. Finally, the resampled signal is downsampled to form a signal having sample rate Fs2.