Abstract: A storage mechanism utilizing a single data recorder from which multiple channels of compressed video data may be simultaneously accessed. The data access to and from the data recorder via a single data access path takes place at a higher data rate (f.sub.1, f.sub.2) than the data rate (f.sub.3, f.sub.4) at which that compressed data needs to be decoded to support a video signal. A video router is used to direct the reproduced data stored within two data channel buffers to respective JPEG decoders where they are decompressed into a signal suitable for driving two digital monitors. In operation, a segment of compressed video data for one channel is recovered from the data recorder and stored within one of the buffers from which it is continuously read at a lower data rate (f.sub.3, f.sub.4). The data recorder then cues to another part of the medium from which data for the second channel is reproduced and stored within another buffer. The process is then repeated.

Abstract: A programmable memory cycle is entered on a keyboard and set by a remote system control processor. Each local processor controls access to memory boards in accordance with the set memory cycle. When the memory cycle is divided into four memory access slots, the processor can provide, in each memory cycle, three read slots and one write slot, two read slots and two write slots, or one read slot and three write slots. When used for processing video signals, the arrangement can process three video channels, or more if expanded by the provision of further memory boards and local processors.

Abstract: In apparatus for spatially interpolating between lines of a digital video signal, to produce interpolated lines, a supersampler horizontally interpolates between samples of the signal to produce a supersampled signal consisting of the original samples and interpolated samples located between them. Block matching circuits each determine, for each sample of the supersampled signal, the extent of matching between two blocks of N.times.M samples (N=number of lines and M=number of samples), the blocks being vertically offset in opposite directions with respect to a line to be interpolated, and being horizontally offset in opposite directions with respect to a predetermined sample position. Each block matching circuit produces a matching value for a respective different horizontal offset.