Patents by Inventor Gavin B. Meil
Gavin B. Meil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Automating addition of power supply rails, fences, and level translators to a modular circuit design
Patent number: 11907634Abstract: A specification for a modular circuit design includes a mapping from global clock domains to global voltage domains. A processor assigns, to a first instance of a clocked primitive component, a global voltage domain based on which global clock domain clocks the first instance, automatically adds, to the modular circuit design, first power supply rails to power the first instance, and connects the first power supply rails from the first instance to a first power supply for a first global voltage domain. The processor assigns, to a second instance of the clocked primitive component, a second global voltage domain based on which global clock domain clocks the second instance, automatically adds second power supply rails to power the second instance, and connects the second power supply rails to a second power supply for a second global voltage domain. The processor may perform further processing on the updated modular circuit design.Type: GrantFiled: September 1, 2021Date of Patent: February 20, 2024Assignee: International Business Machines CorporationInventors: Gavin B. Meil, Kilaus-Dieter Schubert, Benedikt Geukes, Stephen John Barnfield, Maya Safieddine -
AUTOMATING ADDITION OF POWER SUPPLY RAILS, FENCES, AND LEVEL TRANSLATORS TO A MODULAR CIRCUIT DESIGN
Publication number: 20230072459Abstract: A specification for a modular circuit design includes a mapping from global clock domains to global voltage domains. A processor assigns, to a first instance of a clocked primitive component, a global voltage domain based on which global clock domain clocks the first instance, automatically adds, to the modular circuit design, first power supply rails to power the first instance, and connects the first power supply rails from the first instance to a first power supply for a first global voltage domain. The processor assigns, to a second instance of the clocked primitive component, a second global voltage domain based on which global clock domain clocks the second instance, automatically adds second power supply rails to power the second instance, and connects the second power supply rails to a second power supply for a second global voltage domain. The processor may perform further processing on the updated modular circuit design.Type: ApplicationFiled: September 1, 2021Publication date: March 9, 2023Inventors: Gavin B. Meil, Kilaus-Dieter Schubert, Benedikt Geukes, Stephen John Barnfield, Maya Safieddine -
Patent number: 10990725Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine an input sequence of signal transition representations associated with an input net of a component in RTL circuit design, where each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). Determining the input sequence of signal transition representations includes determining that the input sequence of signal transition representations indicates an input gated clock waveform. The design tool also can determine, based on the indicated component and on the input gated clock waveform, an output sequence of signal transition representations derived from the input sequence of signal transition.Type: GrantFiled: May 14, 2019Date of Patent: April 27, 2021Assignee: International Business Machines CorporationInventors: Gabor Drasny, Gavin B. Meil
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Patent number: 10599792Abstract: In some embodiments, a method for processing register transfer level code representing a circuit design can include: determining, by one or more processors based on the register transfer level code, a first group of signal transitions associated with an input net of a component represented in the register transfer level code, wherein each of the group of signal transitions represents a nondeterministic transition from a first signal state to one or more other signal states; determining, at least one of the processors based on the register transfer level code, that a subgroup of signal transitions of the first group is glitch-free; and determining, by at least one of the processors based on the component represented in the register transfer level code and on the subsequence, an output sequence of signal transitions derived from the glitch-free subgroup.Type: GrantFiled: November 27, 2017Date of Patent: March 24, 2020Assignee: International Business Machines CorporationInventors: Gabor Drasny, Gavin B. Meil
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Patent number: 10558782Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of waveforms without simulating the individual waveforms. The tool can determine that a first sequence of signal transition representations of a first signal of the first module comprises a null sequence. The first module of a register level circuit design comprises a second module, the first module and the second module arranged in a hierarchical order. The tool can determine a second sequence of signal transition representations of a second signal of the second module. Signal transition representations of the first signal are for propagation from the first module to the second module using the second signal. The tool can extract a non-null sequence for the first sequence based on the second sequence to generate an extracted first sequence.Type: GrantFiled: May 3, 2019Date of Patent: February 11, 2020Assignee: International Business Machines CorporationInventors: Gabor Drasny, Gavin B. Meil
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Patent number: 10552559Abstract: In some embodiments, a method for processing register transfer level code representing a circuit design. The method can include determining, by one or more processors based on the register transfer level code, an input sequence of signal transitions associated with an input net of a component represented in the register transfer level code, wherein each signal transition represents a nondeterministic transition from a first signal state to one or more possible signal states; determining, at least one of the processors based on the register transfer level code, that a subsequence of signal transitions of the input sequence indicates at most one transition within the subsequence; and determining, by at least one of the processors based on the component represented in the register transfer level code and on the subsequence, an output sequence of signal transitions derived from the input sequence of signal transition.Type: GrantFiled: November 20, 2017Date of Patent: February 4, 2020Assignee: International Business Machines CorporationInventors: Gabor Drasny, Gavin B. Meil
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Patent number: 10552558Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine two or more input sequences of signal transition representations associated with an input net of an indicated component in an RTL circuit design, where the two or more input sequences of signal transition representations are associated with a mode element. Each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). The mode element indicates a selection between two or more output sequences of signal transition representations. It is determined, based on the indicated component and the mode element, two or more output sequences of signal transition representations derived from the input sequence(s) of signal transition representations.Type: GrantFiled: August 31, 2015Date of Patent: February 4, 2020Assignee: International Business Machines CorporationInventors: Gabor Drasny, Gavin B. Meil
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Patent number: 10515164Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine an input sequence of signal transition representations associated with an input net of a component in RTL circuit design, where each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). Determining the input sequence of signal transition representations includes determining that the input sequence of signal transition representations indicates an input gated clock waveform. The design tool also can determine, based on the indicated component and on the input gated clock waveform, an output sequence of signal transition representations derived from the input sequence of signal transition.Type: GrantFiled: November 19, 2014Date of Patent: December 24, 2019Assignee: International Business Machines CorporationInventors: Gabor Drasny, Gavin B. Meil
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Patent number: 10503856Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of waveforms without simulating the individual waveforms. The tool can determine a first sequence of signal transition representations of a first signal of a first module of a register level circuit design. The second module of the register level circuit design comprises the first module, arranged in a hierarchical order. The tool can determine a second sequence of signal transition representations of the first signal of the first module. The signal transition representations of a second signal are propagated from the second module to the first module using the first signal. The tool can determine whether a first mapping can be determined between the first sequence and the second sequence, where the second sequence is propagated through the first module.Type: GrantFiled: March 4, 2016Date of Patent: December 10, 2019Assignee: International Business Machines CorporationInventors: Gabor Drasny, Gavin B Meil
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Publication number: 20190266302Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine an input sequence of signal transition representations associated with an input net of a component in RTL circuit design, where each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). Determining the input sequence of signal transition representations includes determining that the input sequence of signal transition representations indicates an input gated clock waveform. The design tool also can determine, based on the indicated component and on the input gated clock waveform, an output sequence of signal transition representations derived from the input sequence of signal transition.Type: ApplicationFiled: May 14, 2019Publication date: August 29, 2019Inventors: Gabor Drasny, Gavin B. Meil
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Publication number: 20190258772Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of waveforms without simulating the individual waveforms. The tool can determine that a first sequence of signal transition representations of a first signal of the first module comprises a null sequence. The first module of a register level circuit design comprises a second module, the first module and the second module arranged in a hierarchical order. The tool can determine a second sequence of signal transition representations of a second signal of the second module. Signal transition representations of the first signal are for propagation from the first module to the second module using the second signal. The tool can extract a non-null sequence for the first sequence based on the second sequence to generate an extracted first sequence.Type: ApplicationFiled: May 3, 2019Publication date: August 22, 2019Inventors: Gabor Drasny, Gavin B. Meil
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Patent number: 10331822Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine an input sequence of signal transition representations associated with an input net of a component in RTL circuit design, where each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). Determining the input sequence of signal transition representations includes determining that the input sequence of signal transition representations indicates an input gated clock waveform. The design tool also can determine, based on the indicated component and on the input gated clock waveform, an output sequence of signal transition representations derived from the input sequence of signal transition.Type: GrantFiled: August 31, 2015Date of Patent: June 25, 2019Assignee: International Business Machines CorporationInventors: Gabor Drasny, Gavin B. Meil
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Patent number: 10325040Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine two or more input sequences of signal transition representations associated with an input net of an indicated component in an RTL circuit design, where the two or more input sequences of signal transition representations are associated with a mode element. Each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). The mode element indicates a selection between two or more output sequences of signal transition representations. It is determined, based on the indicated component and the mode element, two or more output sequences of signal transition representations derived from the input sequence(s) of signal transition representations.Type: GrantFiled: November 19, 2014Date of Patent: June 18, 2019Assignee: International Business Machines CorporationInventors: Gabor Drasny, Gavin B. Meil
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Patent number: 10325041Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine an input sequence of signal transition representations associated with an input net of a component in a register transfer level circuit design, where each signal transition representation represents a nondeterministic transition from a previous signal state to one or more possible signal states. Determining the input sequence of signal transition representations includes determining that a subsequence of the input sequence of signal transition representations indicates at most one transition within the subsequence of the input sequence.Type: GrantFiled: August 31, 2015Date of Patent: June 18, 2019Assignee: International Business Machines CorporationInventors: Gabor Drasny, Gavin B. Meil
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Patent number: 10318695Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of waveforms without simulating the individual waveforms. The tool can determine that a first sequence of signal transition representations of a first signal of the first module comprises a null sequence. The first module of a register level circuit design comprises a second module, the first module and the second module arranged in a hierarchical order. The tool can determine a second sequence of signal transition representations of a second signal of the second module. Signal transition representations of the first signal are for propagation from the first module to the second module using the second signal. The tool can extract a non-null sequence for the first sequence based on the second sequence to generate an extracted first sequence.Type: GrantFiled: March 4, 2016Date of Patent: June 11, 2019Assignee: International Business Machines CorporationInventors: Gabor Drasny, Gavin B Meil
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Patent number: 10216881Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of waveforms without simulating the individual waveforms. The tool can determine whether module instances of a register level circuit design share a common usage, each instance being associated with a mapping. Two instances share a common usage if a sequence of signal transition representations received by the first instance can be mapped using a first mapping to the same common sequence of signal transition representations as a mapping of another sequence of signal transition representations received by the second instance using a second mapping. A result sequence of signal transition representations was generated by a previous propagation of the common sequence through the common usage. If the two instances share the common usage, the result sequence is mapped to an output sequence for the second instance using the second mapping.Type: GrantFiled: October 23, 2017Date of Patent: February 26, 2019Assignee: International Business Machines CorporationInventors: Gabor Drasny, Gavin B. Meil
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Patent number: 10031987Abstract: Integrated circuits (ICs) rely on static timing analysis during their design to ensure that they will operate at desired frequencies. Delays between sequential elements (e.g., latches and flip-flops) are constrained to meet target clock periods. Certain signals, however, such as untimed nets may be excluded from timing constraints if the circuit function does not require these nets to switch and propagate to sequential elements within the clock period. However, a signal marked as “untimed” may have been mistakenly specified by the designer as an untimed net. To verify that an untimed net does not negatively impact the function of the design logic, the embodiments herein generate upstream and downstream event networks using shadow logic that corresponds to design logic upstream and downstream of the untimed net. A metastability network coupled to these networks is used to model nondeterminism and metastability resulting from transitions or potential glitches on the untimed net.Type: GrantFiled: June 15, 2016Date of Patent: July 24, 2018Assignee: International Business Machines CorporationInventor: Gavin B. Meil
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Publication number: 20180107776Abstract: A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of waveforms without simulating the individual waveforms. The tool can determine whether module instances of a register level circuit design share a common usage, each instance being associated with a mapping. Two instances share a common usage if a sequence of signal transition representations received by the first instance can be mapped using a first mapping to the same common sequence of signal transition representations as a mapping of another sequence of signal transition representations received by the second instance using a second mapping. A result sequence of signal transition representations was generated by a previous propagation of the common sequence through the common usage. If the two instances share the common usage, the result sequence is mapped to an output sequence for the second instance using the second mapping.Type: ApplicationFiled: October 23, 2017Publication date: April 19, 2018Inventors: Gabor Drasny, Gavin B. Meil
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Publication number: 20180082003Abstract: In some embodiments, a method for processing register transfer level code representing a circuit design can include: determining, by one or more processors based on the register transfer level code, a first group of signal transitions associated with an input net of a component represented in the register transfer level code, wherein each of the group of signal transitions represents a nondeterministic transition from a first signal state to one or more other signal states; determining, at least one of the processors based on the register transfer level code, that a subgroup of signal transitions of the first group is glitch-free; and determining, by at least one of the processors based on the component represented in the register transfer level code and on the subsequence, an output sequence of signal transitions derived from the glitch-free subgroup.Type: ApplicationFiled: November 27, 2017Publication date: March 22, 2018Inventors: Gabor Drasny, Gavin B. Meil
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Publication number: 20180075178Abstract: In some embodiments, a method for processing register transfer level code representing a circuit design. The method can include determining, by one or more processors based on the register transfer level code, an input sequence of signal transitions associated with an input net of a component represented in the register transfer level code, wherein each signal transition represents a nondeterministic transition from a first signal state to one or more possible signal states; determining, at least one of the processors based on the register transfer level code, that a subsequence of signal transitions of the input sequence indicates at most one transition within the subsequence; and determining, by at least one of the processors based on the component represented in the register transfer level code and on the subsequence, an output sequence of signal transitions derived from the input sequence of signal transition.Type: ApplicationFiled: November 20, 2017Publication date: March 15, 2018Inventors: Gabor Drasny, Gavin B. Meil