Abstract: Methods and systems that present URLs from a history of records organized by locations are described. Each record may be stored to represent a URL accessed for retrieving a web page by a browser hosted in a device at a certain point in time. Additionally, the record may include a location data indicating a physical location of the device at the certain point in time. Optionally, a timestamp indicating the certain point in time may be included in the record. Groups of the records may be clustered according to the locations. In one embodiment, at least one of the groups may be selected for presentation on a display according to where the display is currently located.

Abstract: Precise exception handling relies on a precise subject state including an accurate program counter and register values of a subject processor. Subject code (17) is translated into target code (21) executable by a target processor (13). The generated target code (17) includes counterpart target instructions (214) associated with fault-vulnerable subject code instructions (174). Further, each of the counterpart target code instruction (214) is associated with recovery information (195). When an exception (e.g. a fault) occurs, the recovery information (195) is retrieved and used to recover a precise subject state, in particular by taking account of optimizations to generate the common-case target code (21). The precise subject state is then used to precisely handle the exception.

Abstract: A dynamic binary translator 19 converts a subject program 17 into target code 21 on a target processor 13. For a multi-threaded subject environment, the translator 19 provides a global token 501 common to each thread 171, 172, and one or more sets of local data 502, which together are employed to coordinate access to a memory 18 as a shared resource. Adjusting the global token 501 allows the local datastructures 502a,b in each thread to detect potential interference with the shared resource 18.

Abstract: A method and apparatus to protect memory consistency in a multiprocessor computing system are described, in particular relating to program code conversion such as dynamic binary translation. The exemplary system provides a memory, processors and a controller/translator unit (CTU) arranged to convert subject code into at least first and second target code portions executable on the processors. The CTU comprises an address space allocation unit to provide virtual address space regions and direct the target code portions to access the memory therethough; a shared memory detection unit to detect a request to access a shared memory area, accessible by both target code portions, and to identify at least one group of instructions in the first target code portion which access the shared memory area; and a memory protection unit to selectively apply memory consistency protection in relation to accesses to the shared memory area by the identified group of instructions.

Abstract: A translator apparatus is provided with both program code interpreting and translating functionality, where subject program code is interpreted rather than being translated in those situations where interpretation of the subject program code is determined to be more beneficial. The translator applies an interpreting algorithm to determine whether a basic block of subject program code should be interpreted or translated. A particular subject of instructions supported by the interpreter functionality is initially selected from an entire instruction set for the subject program code. A basic block will be interpreted 1) if all of the instructions within a basic block are determined to be within the subset of instructions supported by the interpreter functionality, and 2) if an execution count of the basic block is below a translation threshold.

Abstract: A computing system capable of handling floating point operations during program code conversion is described, comprising a processor including a floating point unit and an integer unit. The computing system further comprises a translator unit arranged to receive subject code instructions including at least one instruction relating to a floating point operation and in response to generate corresponding target code for execution on said processor. To handle floating point operations a floating point status unit and a floating point control unit are provided within the translator. These units are cause the translator unit to generate either: target code for performing the floating point operations directly on the floating point unit; or target code for performing the floating point operations indirectly, for example using a combination of the integer unit and the floating point unit. In this way the efficiency of the computing system is improved.

Abstract: A method and apparatus to protect memory consistency in a multiprocessor computing system are described, in particular relating to program code conversion such as dynamic binary translation. The exemplary system provides a memory, processors and a controller/translator unit (CTU) arranged to convert subject code into at least first and second target code portions executable on the processors. The CTU comprises an address space allocation unit to provide virtual address space regions and direct the target code portions to access the memory therethough; a shared memory detection unit to detect a request to access a shared memory area, accessible by both target code portions, and to identify at least one group of instructions in the first target code portion which access the shared memory area; and a memory protection unit to selectively apply memory consistency protection in relation to accesses to the shared memory area by the identified group of instructions.

Abstract: A target computing system performs program code conversion from subject code, executable by a subject computing architecture, into target code executable by the target computing system, and then executes the target code. The target system handles exceptions during binding to native code. Native code binding executes a portion of native code in place of translating a portion of the subject code into the target code. Upon an exception during execution of the portion of native code, the target system saves a target state representing a current point of execution for the portion of native code, and creates a subject state representing an emulated point of execution in the subject architecture. A subject exception handler handles the exception with reference to the subject state. Upon resuming execution from the exception using the subject state, the saved target state is restored to resume execution in the section of portion of native code.

Abstract: A method of handling exceptions during native binding under program code conversion from subject code (17) executable by a subject computing architecture to target code (21) executable by a target computing architecture. Performing native binding executes a portion of native code (28) in place of translating a portion of the subject code (17) into the target code (21). When an exception occurs during the portion of native code (28), the method comprises saving a target state (T?) which represents a current point of execution in the target computing architecture for the portion of native code (28), and creating a subject state (S?) which represents an emulated point of execution in the subject computing architecture.

Abstract: An improved method and apparatus for performing program code conversion is provided and, more particularly, for generating improved intermediate representations for use in program code conversion. During program code conversion, a partial dead code elimination optimization technique is implemented to identify partially dead register definitions within a block of program code being translated. The partial dead code elimination is an optimization to the intermediate representation in the form of code motion for blocks of program code ending in non-computed branches or computed jumps, where target code for all dead child nodes of a partially dead register definition is prevented from being generated and target code for partially dead child nodes of a partially dead register definition is delayed from being generated until after target code is generated for all fully live child nodes for the partially dead register definition.

Abstract: A dynamic binary translator 19 converts a subject program 17 into target code 21 on a target processor 13. For a multi-threaded subject environment, the translator 19 provides a global token 501 common to each thread 171, 172, and one or more sets of local data 502, which together are employed to coordinate access to a memory 18 as a shared resource. Adjusting the global token 501 allows the local datastructures 502a,b in each thread to detect potential interference with the shared resource 18.

Abstract: Precise exception handling relies on a precise subject state including an accurate program counter and register values of a subject processor. Subject code (17) is translated into target code (21) executable by a target processor (13). The generated target code (17) includes counterpart target instructions (214) associated with fault-vulnerable subject code instructions (174). Further, each of the counterpart target code instruction (214) is associated with recovery information (195). When an exception (e.g. a fault) occurs, the recovery information (195) is retrieved and used to recover a precise subject state, in particular by taking account of optimizations to generate the common-case target code (21). The precise subject state is then used to precisely handle the exception.

Abstract: An execution control method is described for use in a translator (19) which converts subject code (17) into target code (21). The translator (19) includes a translator trampoline function (191) which is called from a translator run loop (190) and which in turn calls either to a translator code generator (192) to generate target code, or else calls previously generated target code (212) for execution. Control then returns to the translator trampoline function (191) to make a new call, or returns to the translator run loop (190). Other aspects include making context switches through the trampoline function (191) and setting first and second calling conventions either side of the trampoline function (191). Jumping directly or indirectly between target code blocks (212) during execution is also described.

Abstract: A translator apparatus is provided with both program code interpreting and translating functionality, where subject program code is interpreted rather than being translated in those situations where interpretation of the subject program code is determined to be more beneficial. The translator applies an interpreting algorithm to determine whether a basic block of subject program code should be interpreted or translated. A particular subject of instructions supported by the interpreter functionality is initially selected from an entire instruction set for the subject program code. A basic block will be interpreted 1) if all of the instructions within a basic block are determined to be within the subset of instructions supported by the interpreter functionality, and 2) if an execution count of the basic block is below a translation threshold.

Abstract: An improved method and apparatus for performing program code conversion is provided and, more particularly, for generating improved intermediate representations for use in program code conversion. During program code conversion, a partial dead code elimination optimization technique is implemented to identify partially dead register definitions within a block of program code being translated. The partial dead code elimination is an optimization to the intermediate representation in the form of code motion for blocks of program code ending in non-computed branches or computed jumps, where target code for all dead child nodes of a partially dead register definition is prevented from being generated and target code for partially dead child nodes of a partially dead register definition is delayed from being generated until after target code is generated for all fully live child nodes for the partially dead register definition.