Patents by Inventor Gavin J. Harbison

Gavin J. Harbison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Use of silicide block process to camouflage a false transistor
    Patent number: 8679908
    Abstract: A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: March 25, 2014
    Assignees: HRL Laboratories, LLC, Raytheon Company
    Inventors: Lap-Wai Chow, William M. Clark, Jr., Gavin J. Harbison, James P. Baukus
  • Integrated circuit modification using well implants
    Patent number: 8524553
    Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: September 3, 2013
    Assignee: HRL Laboratories, LLC
    Inventors: Lap-Wai Chow, William M. Clark, Jr., James P Baukus, Gavin J. Harbison
  • Conductive channel pseudo block process and circuit to inhibit reverse engineering
    Patent number: 8258583
    Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: September 4, 2012
    Assignee: HRL Laboratories, LLC
    Inventors: Lap-Wai Chow, William M. Clark, Jr., Gavin J. Harbison, James P. Baukus
  • Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
    Patent number: 8049281
    Abstract: A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when standard voltages are applied to the device.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: November 1, 2011
    Assignee: HRL Laboratories, LLC
    Inventors: Lap-Wai Chow, William M. Clark, Jr., Gavin J. Harbison, Paul Ou Yang
  • Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
    Patent number: 7935603
    Abstract: A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when standard voltages are applied to the device.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: May 3, 2011
    Assignees: HRL Laboratories, LLC, Raytheon Corporation, Promtek
    Inventors: Lap-Wai Chow, William M. Clark, Jr., Gavin J. Harbison, Paul Ou Yang
  • Conductive channel pseudo block process and circuit to inhibit reverse engineering
    Patent number: 7888213
    Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: February 15, 2011
    Assignee: HRL Laboratories, LLC
    Inventors: Lap-Wai Chow, William M. Clark, Jr., Gavin J. Harbison, James P. Baukus
  • INTEGRATED CIRCUIT MODIFICATION USING WELL IMPLANTS
    Publication number: 20090170255
    Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.
    Type: Application
    Filed: March 6, 2009
    Publication date: July 2, 2009
    Applicants: HRL LABORATORIES, LLC, RAYTHEON COMPANY
    Inventors: Lap-Wai Chow, William M. Clark, JR., James P. Baukus, Gavin J. Harbison
  • Integrated circuit modification using well implants
    Patent number: 7514755
    Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: April 7, 2009
    Assignee: HRL Laboratories LLC
    Inventors: Lap-Wai Chow, William M. Clark, Jr., James P. Baukus, Gavin J. Harbison
  • Use of silicon block process step to camouflage a false transistor
    Patent number: 7344932
    Abstract: A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: March 18, 2008
    Assignee: HRL Laboratories, LLC
    Inventors: Lap-Wai Chow, William M. Clark, Jr., Gavin J. Harbison, James P. Baukus
  • Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
    Patent number: 7242063
    Abstract: A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when standard voltages are applied to the device.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: July 10, 2007
    Assignee: HRL Laboratories, LLC
    Inventors: Lap-Wai Chow, William M. Clark, Jr., Gavin J. Harbison, Paul Ou Yang
  • Conductive channel pseudo block process and circuit to inhibit reverse engineering
    Patent number: 7049667
    Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: May 23, 2006
    Assignees: HRL Laboratories, LLC, Raytheon Company
    Inventors: Lap-Wai Chow, William M. Clark, Jr., Gavin J. Harbison, James P. Baukus
  • Use of silicon block process step to camouflage a false transistor
    Patent number: 6979606
    Abstract: A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: December 27, 2005
    Assignees: HRL Laboratories, LLC, Raytheon Company
    Inventors: Lap-Wai Chow, William M. Clark, Jr., Gavin J. Harbison, James P. Baukus
  • Integrated circuit modification using well implants
    Publication number: 20040144998
    Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.
    Type: Application
    Filed: December 12, 2003
    Publication date: July 29, 2004
    Inventors: Lap-Wai Chow, William M. Clark, James P. Baukus, Gavin J. Harbison
  • Use of silicon block process step to camouflage a false transistor
    Publication number: 20040099912
    Abstract: A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.
    Type: Application
    Filed: August 7, 2003
    Publication date: May 27, 2004
    Applicant: HRL LABORATORIES, LLC.
    Inventors: Lap-Wai Chow, William M. Clark, Gavin J. Harbison, James P. Baukus
  • Conductive channel pseudo block process and circuit to inhibit reverse engineering
    Publication number: 20040061186
    Abstract: A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.
    Type: Application
    Filed: August 5, 2003
    Publication date: April 1, 2004
    Inventors: Lap-Wai Chow, William M. Clark, Gavin J. Harbison, James P. Baukus