Abstract: There is disclosed herein current-mode circuitry for measuring a timing difference between first and second signals, the circuitry comprising: a tail node configured during a measurement operation to receive a current pulse in dependence upon the first signal; first and second nodes conductively connectable to said tail node along respective first and second paths; and steering circuitry configured during the measurement operation to control such connections between the tail node and the first and second nodes based on the second signal to steer the current pulse so that a first portion of the current pulse passes along the first path and a second portion of the current pulse passes along the second path in dependence upon the timing difference between said first and second signals; and a signal output unit configured to output a measurement-result signal indicating a measure of said timing difference based upon one or both of the first and second portions.

Abstract: Switching circuitry for use in a digital-to-analog converter, the circuitry comprising: a common node; first and second output nodes; and a plurality of switches connected between the common node and the first and second output nodes and operable in each clock cycle of a series of clock cycles, based on input data, to conductively connect the common node to either the first or second output node along a given one of a plurality of paths, wherein the circuitry is arranged such that a data-controlled switch and a clock-controlled switch are provided in series along each said path from the common node to the first or second output node.

Abstract: There is disclosed herein current-mode circuitry for measuring a timing difference between first and second signals, the circuitry comprising: a tail node configured during a measurement operation to receive a current pulse in dependence upon the first signal; first and second nodes conductively connectable to said tail node along respective first and second paths; and steering circuitry configured during the measurement operation to control such connections between the tail node and the first and second nodes based on the second signal to steer the current pulse so that a first portion of the current pulse passes along the first path and a second portion of the current pulse passes along the second path in dependence upon the timing difference between said first and second signals; and a signal output unit configured to output a measurement-result signal indicating a measure of said timing difference based upon one or both of the first and second portions.

Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

Abstract: Signal-alignment circuitry, comprising: phase-rotation circuitry connected to receive one or more input clock signals and operable to generate therefrom one or more output clock signals; and control circuitry operable to control the amount of phase rotation applied by the phase-rotation circuitry to carry out a plurality of alignment operations, the alignment operations comprising: one or more first operations each comprising rotating one or more of said output clock signals relative to one or more of the other said output clock signals, to bring a phase relationship between said output clock signals, or clock signals derived therefrom, towards or into a given phase relationship; and one or more second operations each comprising rotating all of said output clock signals together, to bring a phase relationship between said output or derived clock signals and said input clock signals or an external-reference signal towards or into a given phase relationship.

Abstract: Signal distribution circuitry for use in an integrated circuit, the signal distribution circuitry comprising: first and second output nodes, for connection to respective output signal lines; first and second supply nodes for connection to respective high and low voltage sources; and switching circuitry connected to the first and second output nodes and the first and second supply nodes and operable based on an input signal to conductively connect the first and second output nodes either to the first and second supply nodes, respectively, in a first state when the input signal has a first value, or to each other, in a second state when the input signal has a second value different from the first value, so as to transmit output signals dependent on the input signal via such output signal lines.

Abstract: A switching circuit, comprising: a main switch having a control terminal; and a clock-path portion connected to the control terminal of the main switch to apply a driving clock signal thereto so as to drive the main switch, wherein the circuit is configured to controllably apply a biasing voltage to the clock-path portion so as to bias a voltage level of the driving clock signal as applied to the control terminal of the main switch.

Abstract: A method of calibrating switching circuitry, the switching circuitry comprising a measurement node and a plurality of output switches connected to the measurement node, and the circuitry being configured, in each clock cycle of a series of clock cycles, to control whether or not one or more of said output switches carry a given current based upon input data, the method comprising: inputting a plurality of different data sequences to the circuitry, each sequence causing a given pattern of voltages to occur at the measurement node as a result of currents passing through the output switches; measuring the voltages occurring at the measurement node for each said sequence; and calibrating the switching circuitry in dependence upon a result of said measuring.

Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

Abstract: Mixed-signal circuitry, comprising: a first switching-circuitry unit for use in an analogue-to-digital converter; and a second switching-circuitry unit for use in a digital-to-analogue converter, wherein: the first switching-circuitry unit is configured to sample an input analogue signal and output a plurality of samples based on a first plurality of clock signals; the second switching-circuitry unit is configured to generate an output analogue signal based on a plurality of data signals and a second plurality of clock signals; and the first and second pluralities of clock signals have the same specifications as one another.

Abstract: A switching circuit, comprising: a main switch having a control terminal; and a clock-path portion connected to the control terminal of the main switch to apply a driving clock signal thereto so as to drive the main switch, wherein the circuit is configured to controllably apply a biasing voltage to the clock-path portion so as to bias a voltage level of the driving clock signal as applied to the control terminal of the main switch.

Abstract: Signal distribution circuitry for use in an integrated circuit, the signal distribution circuitry comprising: first and second output nodes, for connection to respective output signal lines; first and second supply nodes for connection to respective high and low voltage sources; and switching circuitry connected to the first and second output nodes and the first and second supply nodes and operable based on an input signal to conductively connect the first and second output nodes either to the first and second supply nodes, respectively, in a first state when the input signal has a first value, or to each other, in a second state when the input signal has a second value different from the first value, so as to transmit output signals dependent on the input signal via such output signal lines.

Abstract: A method of calibrating switching circuitry, the switching circuitry comprising a measurement node and a plurality of output switches connected to the measurement node, and the circuitry being configured, in each clock cycle of a series of clock cycles, to control whether or not one or more of said output switches carry a given current based upon input data, the method comprising: inputting a plurality of different data sequences to the circuitry, each sequence causing a given pattern of voltages to occur at the measurement node as a result of currents passing through the output switches; measuring the voltages occurring at the measurement node for each said sequence; and calibrating the switching circuitry in dependence upon a result of said measuring.

Abstract: Signal-alignment circuitry, comprising: phase-rotation circuitry connected to receive one or more input clock signals and operable to generate therefrom one or more output clock signals; and control circuitry operable to control the amount of phase rotation applied by the phase-rotation circuitry to carry out a plurality of alignment operations, the alignment operations comprising: one or more first operations each comprising rotating one or more of said output clock signals relative to one or more of the other said output clock signals, to bring a phase relationship between said output clock signals, or clock signals derived therefrom, towards or into a given phase relationship; and one or more second operations each comprising rotating all of said output clock signals together, to bring a phase relationship between said output or derived clock signals and said input clock signals or an external-reference signal towards or into a given phase relationship.

Abstract: Switching circuitry for use in a digital-to-analogue converter, the circuitry comprising: a common node; first and second output nodes; and a plurality of switches connected between the common node and the first and second output nodes and operable in each clock cycle of a series of clock cycles, based on input data, to conductively connect the common node to either the first or second output node along a given one of a plurality of paths, wherein the circuitry is arranged such that a data-controlled switch and a clock-controlled switch are provided in series along each said path from the common node to the first or second output node.

Abstract: Mixed-signal circuitry, comprising: a first switching-circuitry unit for use in an analog-to-digital converter; and a second switching-circuitry unit for use in a digital-to-analog converter, wherein: the first switching-circuitry unit is configured to sample an input analog signal and output a plurality of samples based on a first plurality of clock signals; the second switching-circuitry unit is configured to generate an output analog signal based on a plurality of data signals and a second plurality of clock signals; and the first and second pluralities of dock signals have the same specifications as one another.

Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.