Abstract: A method of forming at least one of a nitride or oxide layer for an integrated circuit, the method comprising: (i) positioning a semiconductor wafer in a processing chamber, the semiconductor wafer including a wafer front side and the processing chamber including differential surfaces adapted to be coupled to a plasma-igniting external radio frequency source; (ii) depositing one of a nitride or oxide on at least an exposed portion of either the semiconductor wafer or a layer affixed relative to the wafer front side by reacting at least two precursor gases for a selected one of the nitride or oxide layer in the chamber while the plasma igniting external radio frequency source is enabled; and (iii) post-treating the one of a nitride or oxide with the plasma igniting external radio frequency source enabled and with exposure to helium and nitrogen in the absence of at least one of the at least two precursor gases.

Abstract: An integrated circuit (IC) including Flash memory cells with self-aligned floating gates and a method of fabrication thereof is disclosed. A floating gate (FG) layer of polysilicon is deposited and patterned to form FG structures as part of a masking block used in forming isolation trenches. A dielectric fill material fills the isolation trenches. Subsequently, the dielectric fill material is removed using a CMP process that is configured to stop on the polysilicon of the FG structures.

Abstract: A sporting footwear having a front sole (21) and heel (23) with the sole having a primary frictional support (30) and the heel having a secondary frictional support (25) which has substantially less frictional support than the primary frictional support.

Abstract: A sporting footwear having a front sole (21) and heel (23) with the sole having a primary frictional support (30) and the heel having a secondary frictional support (25) which has substantially less frictional support than the primary frictional support.