Patents by Inventor GAVIN ZAWALSKI

GAVIN ZAWALSKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10509877
    Abstract: Systems, methods, and products having pipelined inputs to and outputs from an emulator are disclosed. Using a pipeline may allow the round trip cable delay (RTCD) to be spread across two or more clock cycles. In an embodiment, an emulation system may store input data received from a target device during a first clock cycle at a target timing domain interfacing component (TTD), and transmit the stored input data during a second clock cycle after the first clock cycle. In another embodiment, the emulation system may delay transmitting the input data received at the TTD during the first clock cycle such that that the input data reaches the emulator at a predetermined time during the second clock cycle. As the RTCD is spread across multiple clock cycles, the emulation system may implement faster clocks.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: December 17, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mitchell G. Poplack, Viktor Salitrennik, Gavin Zawalski
  • Patent number: 8572529
    Abstract: A method and system for dynamically injecting errors to a user design is disclosed. In one embodiment, the user design having internal states and parameters is run in a design verification system. A reconfigurable design monitor monitors a plurality of error conditions based on the internal states and parameters of the user design and generates a trigger event when a predefined error condition is met. The reconfigurable design monitor transmits a trigger event to an error injector. The error injector injects dynamic errors associated with the triggering event to the user design via a control path to test the user design under the predefined error condition.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: October 29, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Gavin Zawalski, Mark Lewis
  • Publication number: 20120317533
    Abstract: A method and system for dynamically injecting errors to a user design is disclosed. In one embodiment, the user design having internal states and parameters is run in a design verification system. A reconfigurable design monitor monitors a plurality of error conditions based on the internal states and parameters of the user design and generates a trigger event when a predefined error condition is met. The reconfigurable design monitor transmits a trigger event to an error injector. The error injector injects dynamic errors associated with the triggering event to the user design via a control path to test the user design under the predefined error condition.
    Type: Application
    Filed: June 8, 2011
    Publication date: December 13, 2012
    Applicant: Cadence Design Systems, Inc.
    Inventors: GAVIN ZAWALSKI, Mark Lewis