Patents by Inventor Gavri BERGER
Gavri BERGER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12204605Abstract: Systems, methods, and apparatuses relating to a matrix operations accelerator are described.Type: GrantFiled: July 27, 2023Date of Patent: January 21, 2025Assignee: Intel CorporationInventors: Amit Gradstein, Simon Rubanovich, Sagi Meller, Saeed Kharouf, Gavri Berger, Zeev Sperber, Jose Yallouz, Ron Schneider
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Patent number: 12099597Abstract: An apparatus and method for intelligent power virus protection in a processor. For example, one embodiment of a processor comprises: first circuitry including an instruction fetch circuit to fetch instructions, each instruction comprising an instruction type and an associated width comprising a number of bits associated with source and/or destination operand values associated with the instruction; detection circuitry to detect one or more instructions of a particular type and/or width; evaluation circuitry to evaluate an impact of power virus protection (PVP) circuitry when executing the one or more instructions based on the detected instruction types and/or widths; and control circuitry, based on the evaluation, to configure the PVP circuitry in accordance with the evaluation performed by the evaluation circuitry.Type: GrantFiled: October 30, 2023Date of Patent: September 24, 2024Assignee: Intel CorporationInventors: Alexander Gendler, Sagi Meller, Gavri Berger, Igor Yanover
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Publication number: 20240078283Abstract: Systems, methods, and apparatuses relating to a matrix operations accelerator are described.Type: ApplicationFiled: July 27, 2023Publication date: March 7, 2024Inventors: Amit GRADSTEIN, Simon RUBANOVICH, Sagi MELLER, Saeed KHAROUF, Gavri BERGER, Zeev SPERBER, Jose YALLOUZ, Ron SCHNEIDER
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Publication number: 20240061928Abstract: An apparatus and method for intelligent power virus protection in a processor. For example, one embodiment of a processor comprises: first circuitry including an instruction fetch circuit to fetch instructions, each instruction comprising an instruction type and an associated width comprising a number of bits associated with source and/or destination operand values associated with the instruction; detection circuitry to detect one or more instructions of a particular type and/or width; evaluation circuitry to evaluate an impact of power virus protection (PVP) circuitry when executing the one or more instructions based on the detected instruction types and/or widths; and control circuitry, based on the evaluation, to configure the PVP circuitry in accordance with the evaluation performed by the evaluation circuitry.Type: ApplicationFiled: October 30, 2023Publication date: February 22, 2024Inventors: Alexander GENDLER, Sagi MELLER, Gavri BERGER, Igor YANOVER
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Patent number: 11809549Abstract: An apparatus and method for intelligent power virus protection in a processor. For example, one embodiment of a processor comprises: first circuitry including an instruction fetch circuit to fetch instructions, each instruction comprising an instruction type and an associated width comprising a number of bits associated with source and/or destination operand values associated with the instruction; detection circuitry to detect one or more instructions of a particular type and/or width; evaluation circuitry to evaluate an impact of power virus protection (PVP) circuitry when executing the one or more instructions based on the detected instruction types and/or widths; and control circuitry, based on the evaluation, to configure the PVP circuitry in accordance with the evaluation performed by the evaluation circuitry.Type: GrantFiled: December 27, 2019Date of Patent: November 7, 2023Assignee: Intel CorporationInventors: Alexander Gendler, Sagi Meller, Gavri Berger, Igor Yanover
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Publication number: 20230273811Abstract: In one embodiment, an apparatus includes: an instruction fetch circuit to fetch instructions; a decode circuit coupled to the instruction fetch circuit to decode the fetched instructions into micro-operations (pops); a scheduler coupled to the decode circuit to schedule the pops for execution; and an execution circuit coupled to the scheduler, the execution circuit comprising a plurality of execution ports to execute the pops. The scheduler may be configured to: schedule at least some pops of a first type for redundant execution on symmetric execution ports of the plurality of execution ports; and schedule pops of a second type for non-redundant execution on a single execution port of the plurality of execution ports. Other embodiments are described and claimed.Type: ApplicationFiled: February 28, 2022Publication date: August 31, 2023Inventors: Michael Mishaeli, Eyal Oz-Sinay, Gavri Berger, Gal Ofir, Tomer Weiner, Arkady Bramnik
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Patent number: 11714875Abstract: Systems, methods, and apparatuses relating to a matrix operations accelerator are described.Type: GrantFiled: December 28, 2019Date of Patent: August 1, 2023Assignee: Intel CorporationInventors: Amit Gradstein, Simon Rubanovich, Sagi Meller, Saeed Kharouf, Gavri Berger, Zeev Sperber, Jose Yallouz, Ron Schneider
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Publication number: 20230205538Abstract: Embodiments of apparatuses, methods, and systems for adaptive dynamic dispatch of micro-operations are disclosed. In an embodiment, an apparatus includes a plurality of redundant execution units, a dispatcher, control hardware, a first counter, and a second counter. The dispatcher is to dispatch micro-operations to one or more of the plurality of redundant execution units, the micro-operations having a plurality of micro-operation types. The first counter to generate a first count of dispatches, during a window, of micro-operations having a first type of the plurality of micro-operation types. The second counter to generate a second count of dispatches, during the window, of micro-operations having any type of the plurality of micro-operation types. The control hardware is to cause a switch between a first mode and a second mode based in part on the first count and the second count.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Applicant: Intel CorporationInventors: Or Beit Aharon, Zeev Sperber, Gavri Berger, Amit Gradstein, Nofar Hasson
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Patent number: 11409560Abstract: In one embodiment, a processor includes a current protection controller to: receive instruction width information and instruction type information associated with one or more instructions stored in an instruction queue prior to execution of the one or more instructions by an execution circuit; determine a power license level for the core based on the corresponding instruction width information and the instruction type information; generate a request for a license for the core corresponding to the power license level; and communicate the request to a power controller when the one or more instructions are non-speculative, and defer communication of the request when at least one of the one or more instructions is speculative. Other embodiments are described and claimed.Type: GrantFiled: March 28, 2019Date of Patent: August 9, 2022Assignee: Intel CorporationInventors: Krishnamurthy Jambur Sathyanarayana, Robert Valentine, Alexander Gendler, Shmuel Zobel, Gavri Berger, Ian M. Steiner, Nikhil Gupta, Eyal Hadas, Edo Hachamo, Sumesh Subramanian
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Patent number: 11385704Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.Type: GrantFiled: February 24, 2021Date of Patent: July 12, 2022Assignee: Intel CorporationInventors: Alexander Gendler, Igor Yanover, Gavri Berger, Edo Hachamo, Elkana Korem, Hanan Shomroni, Daniela Kaufman, Lev Makovsky, Haim Granot
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Publication number: 20210271305Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.Type: ApplicationFiled: February 24, 2021Publication date: September 2, 2021Inventors: Alexander Gendler, Igor Yanover, Gavri Berger, Edo Hachamo, Elkana Korem, Hanan Shomroni, Daniela Kaufman, Lev Makovsky, Haim Granot
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Publication number: 20210200860Abstract: An apparatus and method for intelligent power virus protection in a processor. For example, one embodiment of a processor comprises: first circuitry including an instruction fetch circuit to fetch instructions, each instruction comprising an instruction type and an associated width comprising a number of bits associated with source and/or destination operand values associated with the instruction; detection circuitry to detect one or more instructions of a particular type and/or width; evaluation circuitry to evaluate an impact of power virus protection (PVP) circuitry when executing the one or more instructions based on the detected instruction types and/or widths; and control circuitry, based on the evaluation, to configure the PVP circuitry in accordance with the evaluation performed by the evaluation circuitry.Type: ApplicationFiled: December 27, 2019Publication date: July 1, 2021Inventors: ALEXANDER GENDLER, SAGI MELLER, GAVRI BERGER, IGOR YANOVER
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Patent number: 10942738Abstract: The present disclosure is directed to systems and methods for performing one or more operations on a two dimensional tile register using an accelerator that includes a tiled matrix multiplication unit (TMU). The processor circuitry includes reservation station (RS) circuitry to communicatively couple the processor circuitry to the TMU. The RS circuitry coordinates the operations performed by the TMU. TMU dispatch queue (TDQ) circuitry in the TMU maintains the operations received from the RS circuitry in the order that the operations are received from the RS circuitry. Since the duration of each operation is not known prior to execution by the TMU, the RS circuitry maintains shadow dispatch queue (RS-TDQ) circuitry that mirrors the operations in the TDQ circuitry.Type: GrantFiled: March 29, 2019Date of Patent: March 9, 2021Assignee: Intel CorporationInventors: Zeev Sperber, Amit Gradstein, Simon Rubanovich, Igor Yanover, Gavri Berger, Eyal Hadas, Saeed Kharouf, Ron Schneider, Sagi Meller, Jose Yallouz
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Patent number: 10936041Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.Type: GrantFiled: March 29, 2019Date of Patent: March 2, 2021Assignee: Intel CorporationInventors: Alexander Gendler, Igor Yanover, Gavri Berger, Edo Hachamo, Elkana Korem, Hanan Shomroni, Daniela Kaufman, Lev Makovsky, Haim Granot
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Publication number: 20200310794Abstract: The present disclosure is directed to systems and methods for performing one or more operations on a two dimensional tile register using an accelerator that includes a tiled matrix multiplication unit (TMU). The processor circuitry includes reservation station (RS) circuitry to communicatively couple the processor circuitry to the TMU. The RS circuitry coordinates the operations performed by the TMU. TMU dispatch queue (TDQ) circuitry in the TMU maintains the operations received from the RS circuitry in the order that the operations are received from the RS circuitry. Since the duration of each operation is not known prior to execution by the TMU, the RS circuitry maintains shadow dispatch queue (RS-TDQ) circuitry that mirrors the operations in the TDQ circuitry.Type: ApplicationFiled: March 29, 2019Publication date: October 1, 2020Applicant: Intel CorporationInventors: ZEEV SPERBER, Amit Gradstein, Simon Rubanovich, Igor Yanover, Gavri Berger, Eyal Hadas, Saeed Kharouf, Ron Schneider, Sagi Meller, Jose Yallouz
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Publication number: 20200310872Abstract: In one embodiment, a processor includes a current protection controller to: receive instruction width information and instruction type information associated with one or more instructions stored in an instruction queue prior to execution of the one or more instructions by an execution circuit; determine a power license level for the core based on the corresponding instruction width information and the instruction type information; generate a request for a license for the core corresponding to the power license level; and communicate the request to a power controller when the one or more instructions are non-speculative, and defer communication of the request when at least one of the one or more instructions is speculative. Other embodiments are described and claimed.Type: ApplicationFiled: March 28, 2019Publication date: October 1, 2020Inventors: Krishnamurthy Jambur Sathyanarayana, Robert Valentine, Alexander Gendler, Shmuel Zobel, Gavri Berger, Ian M. Steiner, Nikhil Gupta, Eyal Hadas, Edo Hachamo, Sumesh Subramanian
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Publication number: 20200310511Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.Type: ApplicationFiled: March 29, 2019Publication date: October 1, 2020Inventors: Alexander Gendler, Igor Yanover, Gavri Berger, Edo Hachamo, Elkana Korem, Hanan Shomroni, Daniela Kaufman, Lev Makovsky, Haim Granot
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Publication number: 20200201932Abstract: Systems, methods, and apparatuses relating to a matrix operations accelerator are described.Type: ApplicationFiled: December 28, 2019Publication date: June 25, 2020Inventors: Amit GRADSTEIN, Simon RUBANOVICH, Sagi MELLER, Saeed KHAROUF, Gavri BERGER, Zeev SPERBER, Jose YALLOUZ, Ron SCHNEIDER
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Patent number: 9996127Abstract: A processor and method are described for performing proactive throttling of execution unit ports. For example, one embodiment of a processor core comprises: a plurality of execution unit ports within an execution stage of the processor core; a scheduler unit to schedule execution of a plurality of operations to the plurality of execution unit ports; and proactive throttling logic to limit acceleration of execution of the operations by the ports to an acceleration level which does not result in significant power supply droops.Type: GrantFiled: March 12, 2014Date of Patent: June 12, 2018Assignee: Intel CorporationInventors: Omer Vikinski, Igor Yanover, Gavri Berger, Gabi Malka, Zeev Sperber
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Patent number: 9292362Abstract: In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to determine a first event count associated with events of a first type that have occurred since a start of a first defined interval. The first core also includes a second event counter to determine a second event count associated with events of a second type that have occurred since the start of the first defined interval, and stall logic to stall execution of operations including at least first operations associated with events of the first type, until the first defined interval is expired responsive to the first event count exceeding a first combination threshold concurrently with the second event count exceeding a second combination threshold. Other embodiments are described and claimed.Type: GrantFiled: June 25, 2013Date of Patent: March 22, 2016Assignee: Intel CorporationInventors: Lev Makovsky, Zeev Sperber, Efraim Rotem, Nir Rosenzweig, Stanislav Shwartsman, Raanan Sade, Igor Yanover, Gavri Berger, Tomer Weiner, Ron Gabor