Abstract: An integrated circuit device includes general purpose input/output (I/O) circuitry having a transmit level shifter circuit in a transmit I/O circuit and a receive level shifter circuit in a receive I/O circuit. The integrated circuit device also includes an I/O pad which couples an output of the transmit level shifter circuit to an input of the receive level shifter circuit, a counter circuit, an inverter circuit coupled between the receive level shifter circuit and the counter circuit, and a logic gate. The logic gate includes a first input coupled to an output of the inverter circuit, a second input coupled to a counter_done signal from the counter circuit, and an output coupled to provide a data_out signal to an input of the transmit level shifter circuit.

Abstract: An integrated circuit (IC) includes an input/output (IO) circuit in a first power domain, coupled between a first and second power supply terminal, and an integrity monitor in a second power domain, coupled between a third and fourth power supply terminal. The IO circuit includes an external terminal configured to communicate signals external to the IC, and an internal circuit node configured to provide a tap signal, wherein the internal circuit node is neither the first power supply terminal nor the second power supply terminal. The integrity monitor has a counter configured to provide a count value by counting each time the tap signal reaches a threshold voltage, and is configured to provide an integrity fault indicator based at least in part on the count value, in which the integrity fault indicator indicates whether or not a signal provided or received by the external terminal is trustworthy.

Abstract: An integrated circuit device includes general purpose input/output (I/O) circuitry having a transmit level shifter circuit in a transmit I/O circuit and a receive level shifter circuit in a receive I/O circuit. The integrated circuit device also includes an I/O pad which couples an output of the transmit level shifter circuit to an input of the receive level shifter circuit, a counter circuit, an inverter circuit coupled between the receive level shifter circuit and the counter circuit, and a logic gate. The logic gate includes a first input coupled to an output of the inverter circuit, a second input coupled to a counter_done signal from the counter circuit, and an output coupled to provide a data_out signal to an input of the transmit level shifter circuit.

Abstract: Disclosed is a control circuit for protecting MOSFETs in I/O buffers or other devices from overvoltage damage, especially during power ramp up. The control circuit can perform additional functions. In one embodiment an integrated circuit (IC) includes input/output (I/O) buffers coupled to an output supply voltage terminal that is configured to receive an output supply voltage Vddio. Each of the I/O buffers has a bias voltage generator that is configured to generate a first bias voltage with a magnitude that depends on a control signal; an output stage that receives the first bias voltage, wherein the output stage is configured to drive an I/O pad based upon a data signal received at the I/O buffer. The IC also includes an I/O buffer controller coupled to the I/O buffers and configured to generate the control signal based upon a magnitude of the output supply voltage Vddio.

Abstract: An integrated circuit (IC) includes an input/output (IO) circuit in a first power domain, coupled between a first and second power supply terminal, and an integrity monitor in a second power domain, coupled between a third and fourth power supply terminal. The IO circuit includes an external terminal configured to communicate signals external to the IC, and an internal circuit node configured to provide a tap signal, wherein the internal circuit node is neither the first power supply terminal nor the second power supply terminal. The integrity monitor has a counter configured to provide a count value by counting each time the tap signal reaches a threshold voltage, and is configured to provide an integrity fault indicator based at least in part on the count value, in which the integrity fault indicator indicates whether or not a signal provided or received by the external terminal is trustworthy.

Abstract: Disclosed is a control circuit for protecting MOSFETs in I/O buffers or other devices from overvoltage damage, especially during power ramp up. The control circuit can perform additional functions. In one embodiment an integrated circuit (IC) includes input/output (I/O) buffers coupled to an output supply voltage terminal that is configured to receive an output supply voltage Vddio. Each of the I/O buffers has a bias voltage generator that is configured to generate a first bias voltage with a magnitude that depends on a control signal; an output stage that receives the first bias voltage, wherein the output stage is configured to drive an I/O pad based upon a data signal received at the I/O buffer. The IC also includes an I/O buffer controller coupled to the I/O buffers and configured to generate the control signal based upon a magnitude of the output supply voltage Vddio.

Abstract: A memory circuit includes a plurality of memory tiles. Each memory tile in the plurality of memory tiles includes a plurality of bit cells and a control circuit coupled to the plurality of bit cells. The control circuit is configured to provide latched data to the plurality of bit cells during write operations. A first write control line is coupled to the control circuit in a first memory tile, and the first write control line is configured to initiate a first write operation in the first memory tile. And a second write control line is coupled to the control circuit in a second memory tile, and the second write control line configured to initiate a second write operation in the second memory tile. The second write operation may be initiated before the first write operation is completed.

Abstract: A memory circuit includes a plurality of memory tiles. Each memory tile in the plurality of memory tiles includes a plurality of bit cells and a control circuit coupled to the plurality of bit cells. The control circuit is configured to provide latched data to the plurality of bit cells during write operations. A first write control line is coupled to the control circuit in a first memory tile, and the first write control line is configured to initiate a first write operation in the first memory tile. And a second write control line is coupled to the control circuit in a second memory tile, and the second write control line configured to initiate a second write operation in the second memory tile. The second write operation may be initiated before the first write operation is completed.

Abstract: Receivers for memory interfaces and related methods are disclosed having pulsed control of input signal attenuation networks. Embodiments include a DC common mode attenuation network, an AC coupling network, a pulse generator, and an amplifier. The pulse generator receives the output of the amplifier and generates a pulse signal that in part controls the operation of the attenuation network. The attenuation network generates an attenuated signal having reduced DC common mode levels. This attenuated signal is combined with an AC component passed by the AC coupling network. The resulting combined signal is detected and amplified by the amplifier. Different voltage domains are used for the attenuation network and the AC coupling network as compared to the amplifier and the pulse generator. By attenuating DC common mode levels while maintaining AC signal levels, the disclosed embodiments allow for proper signal detection over a wide range of DC common mode levels.

Abstract: Receivers for memory interfaces and related methods are disclosed having pulsed control of input signal attenuation networks. Embodiments include a DC common mode attenuation network, an AC coupling network, a pulse generator, and an amplifier. The pulse generator receives the output of the amplifier and generates a pulse signal that in part controls the operation of the attenuation network. The attenuation network generates an attenuated signal having reduced DC common mode levels. This attenuated signal is combined with an AC component passed by the AC coupling network. The resulting combined signal is detected and amplified by the amplifier. Different voltage domains are used for the attenuation network and the AC coupling network as compared to the amplifier and the pulse generator. By attenuating DC common mode levels while maintaining AC signal levels, the disclosed embodiments allow for proper signal detection over a wide range of DC common mode levels.

Abstract: A phase locked loop having a normal mode and a burn-in mode. The logic portion is coupled to a logic power supply terminal and includes a clock receiver coupled to a phase frequency detector. The analog portion has a charge pump coupled to the phase frequency detector and to an analog power supply terminal. The analog portion also has a voltage controlled oscillator coupled to the charge pump at an analog node and to the analog power supply terminal. The phase locked loop has a node control circuit that is coupled to the analog node during the burn-in mode that controls a voltage at the analog node sufficiently below a voltage at the analog power supply terminal to avoid over-stressing the charge pump and the voltage controlled oscillator during the burn-in mode.

Abstract: A voltage translation circuit (116) provides an output analog voltage signal that has a translated voltage of the voltage of an input analog voltage signal over a range of values of the input analog voltage signal. The voltage translation circuit includes an input stage (202) having a circuit node and an input transistor (210) coupled between the circuit node and a power supply terminal, wherein a gate of the input transistor is coupled to receive the input analog voltage signal; a current path circuit (204) in parallel with the input transistor, wherein the current path includes a first transistor coupled between the circuit node and the power supply terminal; and a circuit coupled to provide a variable body bias voltage to a body of the first transistor.

Abstract: A voltage translation circuit (116) provides an output analog voltage signal that has a translated voltage of the voltage of an input analog voltage signal over a range of values of the input analog voltage signal. The voltage translation circuit includes an input stage (202) having a circuit node and an input transistor (210) coupled between the circuit node and a power supply terminal, wherein a gate of the input transistor is coupled to receive the input analog voltage signal; a current path circuit (204) in parallel with the input transistor, wherein the current path includes a first transistor coupled between the circuit node and the power supply terminal; and a circuit coupled to provide a variable body bias voltage to a body of the first transistor.

Abstract: A phase locked loop having a normal mode and a burn-in mode. The logic portion is coupled to a logic power supply terminal and includes a clock receiver coupled to a phase frequency detector. The analog portion has a charge pump coupled to the phase frequency detector and to an analog power supply terminal. The analog portion also has a voltage controlled oscillator coupled to the charge pump at an analog node and to the analog power supply terminal. The phase locked loop has a node control circuit that is coupled to the analog node during the burn-in mode that controls a voltage at the analog node sufficiently below a voltage at the analog power supply terminal to avoid over-stressing the charge pump and the voltage controlled oscillator during the burn-in mode.

Abstract: A level shifter includes first, second and third capacitively configured transistors, first and second switching transistors, and an inverting circuit. The first capacitively configured transistor has a first terminal that receives an input signal. Second and third capacitively configured transistor each have first terminal coupled to a second terminal of the first capacitively configured transistor. The second capacitively configured transistor is coupled in series with a first switching transistor that is also coupled to a first power supply terminal. The third capacitively configured transistor is coupled in series with a second switching transistor that is also coupled to a second power supply terminal.

Abstract: A phase locked loop (PLL) includes a phase frequency detector powered by a first analog supply voltage; a charge pump powered by a second analog supply voltage, different from the first analog supply voltage; a voltage controlled oscillator (VCO) powered by a third analog supply voltage, different from the first and second analog supply voltages, wherein a frequency of the VCO is controlled by a control voltage; and a supply voltage provider having a first circuit node coupled to a fourth analog supply voltage, a second circuit node which provides the first analog supply voltage, a third circuit node which provides the second analog supply voltage, and a fourth circuit node which provides the third analog supply voltage, and a current compensator coupled to one of the second, third, or fourth circuit nodes, wherein the current compensator provides a variable current draw based on the control voltage.

Abstract: A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal provided to a device module. The phase detector provides a pulse having a width indicative of the phase difference. If the phase difference exceeds one of a plurality of threshold values, an indicator can be asserted. Based on the indicator, a control module can take remedial action, such as providing a different clock signal to the device module or triggering an interrupt at a processor device.

Abstract: A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal of the phase locked loop. The phase detector provides a pulse having a width indicative of the phase difference. A phase measurement module determines a digital value based on the pulse width. Accordingly, the digital value provides an indication of the phase difference between the reference clock signal and the output clock signal. A series of the digital values can be recorded to indicate how the phase difference varies over time, thereby providing a useful characterization of device behavior.

Abstract: A phase-locked loop (PLL) system including a phase-frequency detector for generating an up signal or a down signal based on a phase difference between a reference clock and a feedback clock is provided. The PLL system further includes a phase-error spreading circuit for generating phase-spread pulses based on a relationship between a first time attribute of the up signal or the down signal and a second time attribute of the phase-spread pulses. The PLL system further includes a voltage-controlled oscillator (VCO) for generating a VCO clock based on the phase-spread pulses. The PLL system may also include a charge pump that generates a pumping signal based on the phase-spread pulses.

Abstract: A method for a phase-locked loop (PLL) in an integrated circuit, wherein the PLL comprises a voltage-controlled oscillator (VCO). The method includes, in a training mode: (1) setting a control voltage of the VCO at a first voltage level; (2) increasing the control voltage of the VCO from the first voltage level to a second voltage level, until a loss of the feedback signal is detected; and (3) storing an indicator value corresponding to the second voltage level of the control voltage of the VCO. The method further includes, in a normal mode: (1) monitoring a voltage level of the control voltage of the VCO by generating a monitored indicator value corresponding to the voltage level of the control voltage of the VCO; and (2) asserting the loss of feedback signal based on a comparison of the monitored indicator value and the indicator value.