Patents by Inventor Gayatri Gopalan

Gayatri Gopalan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Electrostatic discharge power clamp trigger circuit using low stress voltage devices
    Patent number: 8102632
    Abstract: Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: January 24, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yikai Liang, Arvind Bomdica, Samudyatha Suryanarayana, Gayatri Gopalan, Min Xu, Xin Liu, Ming-Ju Edward Lee
  • Power supply equalization circuit using distributed high-voltage and low-voltage shunt circuits
    Patent number: 8102633
    Abstract: Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages, or other excessive current conditions. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin, a voltage drop network to drop a high voltage on the IO pin to a low voltage level on a floating voltage rail, a first shunt circuit coupled between the floating supply rail and ground, an equalizer circuit coupled between the floating supply rail and a low voltage supply rail, and a second shunt circuit coupled to the equalizer circuit through the low voltage supply rail.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: January 24, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yikai Liang, Arvind Bomdica, Samudyatha Suryanarayana, Gayatri Gopalan, Min Xu, Xin Liu, Ming-Ju Edward Lee
  • Electrostatic Discharge Power Clamp Trigger Circuit Using Low Stress Voltage Devices
    Publication number: 20100238598
    Abstract: Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices.
    Type: Application
    Filed: March 18, 2009
    Publication date: September 23, 2010
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Yikai Liang, Arvind Bomdica, Samudyatha Suryanarayana, Gayatri Gopalan, Min Xu, Xin Liu, Ming-Ju Edward Lee
  • Power Supply Equalization Circuit Using Distributed High-Voltage and Low-Voltage Shunt Circuits
    Publication number: 20100238599
    Abstract: Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages, or other excessive current conditions. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin, a voltage drop network to drop a high voltage on the IO pin to a low voltage level on a floating voltage rail, a first shunt circuit coupled between the floating supply rail and ground, an equalizer circuit coupled between the floating supply rail and a low voltage supply rail, and a second shunt circuit coupled to the equalizer circuit through the low voltage supply rail.
    Type: Application
    Filed: March 18, 2009
    Publication date: September 23, 2010
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Yikai Liang, Arvind Bomdica, Samudyatha Suryanarayana, Gayatri Gopalan, Min Xu, Xin Liu, Ming-Ju Edward Lee