Abstract: A method and resulting device that eliminates vertical steps or gaps in a deep trench isolation region and, thus, eliminates or drastically reduces a possibility of polysilicon stringers. Additionally, the invention allows an inexpensive dielectric material, for example a lower-quality silicon dioxide to be used to fill the deep trench and a higher quality oxide, in an electrically active region, to be used on an uppermost portion of the deep trench without affecting device performance or increasing a possibility of forming polysilicon stringers.

Abstract: Methods and materials for silicon on insulator wafer production in which the doping concentration in a handle wafer is sufficiently high to inhibit dopant from diffusing from the bond wafer during or after bonding to the handle wafer.

Abstract: By aligning the primary flat of a wafer with a (100) plane rather than a (110) plane, devices can be formed with primary currents flowing along the (100) plane. In this case, the device will intersect the (111) plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation/relief along the (111) direction and consequently reduces defects as well as leakage and parasitic currents. The leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique the leakage current is reduced by up to two orders of magnitude for an N-channel CMOS device.

Abstract: A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.

Abstract: A method for forming a self-aligned twin well region is provided. The method includes implanting a first well type doping species into the DHL such that its distribution remains stopped in the DHL above the silicon substrate, etching away a portion of the DHL using a photoresist mask, implanting a second well type doping species into the portions of the silicon substrate exposed by the etching, and moving a portion of the first well type doping species into the silicon substrate.

Abstract: A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO stack forming a first alignment artifact. A second mask layer is applied after removing the first mask layer. A second well doping occurs at second mask layer etching sites to maintain clearance between the two wells within active areas and provide an overlap of the two wells in a frame area. At the first alignment artifact in the overlap of the two wells, further etchings remove remaining layers of the ONO stack and remove silicon from the upper most layer of the semiconductor forming a second registration mark, which may be covered by a protective layer.

Abstract: A method and resulting device that eliminates vertical steps or gaps in a deep trench isolation region and, thus, eliminates or drastically reduces a possibility of polysilicon stringers. Additionally, the invention allows an inexpensive dielectric material, for example a lower-quality silicon dioxide to be used to fill the deep trench and a higher quality oxide, in an electrically active region, to be used on an uppermost portion of the deep trench without affecting device performance or increasing a possibility of forming polysilicon stringers.

Abstract: A method and system for providing a twin well in a semiconductor device is described. The method and system include masking a first portion of the device such that a second portion of the device is exposed. A sacrificial layer has a first portion on the first portion of the device and a second portion on the second portion of the device. In one aspect, an oxidation stop layer may be below the sacrificial layer. The method and system include implanting a first well in the second portion of the device, exposing the first portion of the device after the first well is implanted, and oxidizing the second portion of sacrificial layer after the exposing. The method and system further include implanting the second well in the first portion of the device after the oxidizing and planarizing the device after the second well is implanted.

Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure comprises an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure. A system and method in accordance with the present invention utilizes a LDNMOS transistor as ESD protection element with optimised substrate contacts. The ratio of substrate contact rows to drain contact rows is smaller than one in order to reduce the triggering voltage of the inherent bipolar transistor.

Abstract: A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO stack forming a first alignment artifact. A second mask layer is applied after removing the first mask layer. A second well doping occurs at second mask layer etching sites to maintain clearance between the two wells within active areas and provide an overlap of the two wells in a frame area. At the first alignment artifact in the overlap of the two wells, further etchings remove remaining layers of the ONO stack and remove silicon from the upper most layer of the semiconductor forming a second registration mark, which may be covered by a protective layer.

Abstract: A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.

Abstract: A protective envelope for a chip card wherein a fabric sheath with a top flap allows entry of the chip card. An inner Faraday cage, nested within the fabric sheath, made of wire mesh or thin foil prevents electromagnetic fields from penetrating the sheath once the top flap is closed on the sheath body.

Abstract: A method of fabricating an integrated circuit using photolithography and an antireflective coating. An antireflective coating is formed on a substrate wherein the antireflective coating is electrically polarizable. A photoresist coating is formed on the antireflective coating on a side opposite from the substrate and the photoresist is exposed to activating radiation. The antireflective coating is subjected to an applied electric field at substantially the same time as the photoresist is exposed to activating radiation. The radiation absorption coefficient of said antireflective coating is increased and the refractive index of said antireflective coating is changed to be substantially equal to the refractive index of said photoresist coating.

Abstract: An integrated circuit includes a vertical-interdigitated capacitor located between an upper interconnect layer and a lower interconnect layer. Both interconnect layers include conductors formed of a metal capable of atom diffusion or ion migration, such as copper. The capacitor plates contact an interconnect layer conductor to create barrier layers to prevent atom diffusion or ion migration from the conductors at the contact locations. Additional barrier layers contact the conductors at locations other than where the capacitor plate portions contact the conductors, and the additional barrier layers are preferably formed of the same material and at the same time that one of the plates is formed. The integrated circuit may include a via plug interconnect extending between conductors of upper and lower interconnect layers, with a plug barrier layer surrounding the plug material to prevent atom diffusion or ion migration from the plug material.

Abstract: A method of fabricating an integrated circuit using photolithography and an antireflective coating. An antireflective coating is formed on a substrate wherein the antireflective coating is electrically polarizable. A photoresist coating is formed on the antireflective coating on a side opposite from the substrate and the photoresist is exposed to activating radiation. The antireflective coating is subjected to an applied electric field at substantially the same time as the photoresist is exposed to activating radiation. The radiation absorption coefficient of said antireflective coating is increased and the refractive index of said antireflective coating is changed to be substantially equal to the refractive index of said photoresist coating.

Abstract: MOS functional devices and electrostatic discharge protection devices are formed on a substrate having a relatively low-resistance area beneath the functional devices to inhibit latch-up of the functional devices and a relatively high resistance area beneath each electrostatic protection device to reduce the snapback holding voltage of each electrostatic discharge protection device.

Abstract: A monolithic semiconductor device includes a field effect transistor and a bipolar junction transistor with a pillar emitter structure. The pillar structure raises the BJT emitter above the surface of a trenched base. Ions implanted into the base trench diffuses into an extrinsic base contact region. The pillar elevation structure increases travel distance between the trench and the emitter and protects against encroachment without increasing the total emitter area allocated to the BJT device. A spacer oxide adjacent to the pillar separates the pillar from the trench-region implanted with ions.