Abstract: Techniques and systems for design of optical switch arrays so as to minimize power requirements are described. A design system includes a computer system hosting a design program. The design program receives parameters for the switch array, including a number N of outputs required, and either a maximum number L of stages allowed or maximum and average power requirements allowed. If power requirements are used as parameters, the design program uses N and the power requirements to compute the value of L. The design program then constructs a minimum power sequence of L switches or N switches, whichever is less. If N is less than L+1, N outputs are present and the array is complete. If N is greater than L+1, the design program then adds switches one at a time to the minimum power switch path of the array, until the array provides N outputs.

Abstract: An optical transmission system formed from a plurality of nodes interconnected in a ring configuration via at least two transmission media provides protection capacity for each optical channel. If a channel signal does not meet predetermined criteria, then a loss of signal indication is declared for the channel and one of a plurality of protection switching states is invoked to re-route service traffic carried by the impaired channel to its destination via corresponding protection capacity. The switching states include particular transmission states and at least “keep-alive” and “protection access” states.

Abstract: A method and apparatus for encoding and decoding m-bit groups of digital data, where m is at least eight, into serial n bit groups such that each encoded serial n-bit group has sufficient data transitions therein to maintain the synchronization of a phase locked loop clock recovery circuit in a high speed serial link of a communication path. Further, this method and apparatus provides a duty cycle that is within an operational range of the ideal 50 percent, which reduces voltage drift of a.c. coupled high speed serial data links, or reduces thermal drift of optically coupled high speed serial data links.

Abstract: A new dimension for growth is presented for the generalized growable packet switch architecture. That dimension is time and by rolling routing requests around a distributed out-of-band controller ring, ATM cell traffic can be controlled and spread across two time intervals. The rolling of routing requests and the resulting time spreading of the cell traffic through the distribution network averages out bursts and localized hot spots, thereby reducing blocking and improving cell loss probabilities with only small increases in hardware cost and complexity.

Abstract: A physically realizable one terabit or more ATM packet switch that has a large number of input interfaces connected to a single stage switching fabric which is in turn connected to a number of output modules, generally according to the growable packet switch architecture. This ATM packet switch is different from other growable packet switches in that it has a single stage switch fabric controlled by an out-of-band controller, yet it has significantly reduced complexity with respect to comparably sized electronic crossbar switches or their isomorphs.

Abstract: A telecommunications switch which has a central switch fabric made up of multiple crossbars that can be used to switch either circuit switched or packet switch communications as long as appropriate input and output interfaces and controllers are provided. Thus, a large, high throughput telecommunications switch is provided where the expensive switch fabric core can remain the same and the interfaces and control cards changed as the relative demands for circuit switched communications and packet switched communications, such as ATM, evolve. Besides being flexible, this switch may also be fault tolerant.

Abstract: A growable packet switching arrangement where the distribution network blocking probability is substantially reduced because the network has both switch links and chute links, and the network nodes include both a switching element interconnecting successive stage switch links and a plurality of non-switching, chute connections interconnecting successive stage chute links. A network node can transfer a packet, being received on a switch link, to any selected one of the chute connections of that node for transmission on a chute link. The network nodes are relatively simple and inexpensive because they store only the first few bits needed to route an ATM cell. The blocking probability is further reduced when the number of chutes per node is increased. The number of chutes may be based, for example, on the number of switch link inputs per node.

Abstract: In a time-space-time switching network that provides connections at a hierarchy of data rates, a path-hunt arrangement effects establishment of a switched connection of a given bandwidth as a collection of a plurality of connections of smaller bandwidths of different sizes. Connections are first found at the highest rate of the hierarchy to satisfy as much of the given bandwidth as possible. Then, connections are found at the lower rates to satisfy any remaining unsatisfied bandwidth. The path-hunt uses a hierarchy of status tables, corresponding to the hierarchy of rates, for each time-switching element of the network. The tables have entries that define availability of time slots--representing bandwidth of the tables' corresponding rates--between that time-switching element and a space-switching stage of the network. Connections are provided at the highest rate by finding matching idle time-slot entries in the high rate status tables for the two time-switching elements involved in the connection.

Abstract: A growable packet switching arrangement where the number, S, of distribution network stages is reduced by bounding S according to log.sub.2 (max(L,N))<S+1<[log.sub.2 (max(L,N))].sup.2 /2. Since the distribution network is made up of stages of opto-electronic nodes and interconnecting free-space optical link stages, there is no need to transmit input signals using different frequencies. Input signals are instead distinguished based on their spatial location. Accordingly, there is no receiver tunability restriction on L, the number of inputs. Further, because signals are regenerated at each network stage and there is only a 3:1 power loss (approximate) at a given stage, high signal/noise ratios and corresponding low bit error rates are achieved.

Abstract: A low blocking packet distribution network which is implemented in optics. The network has both switch links and chute links, and the network nodes include both a switching devices interconnecting successive stage switch links and a plurality of non-switching, chute connections interconnecting successive stage chute links. A network node can transfer a packet, being received on a switch link, to any selected one of the chute connection means of that node for transmission on a chute links. The network nodes are relatively simple and inexpensive because they store only the first few bits needed to route an ATM cell. The blocking probability is further reduced when the number of chutes per node is increased. The number of chutes may be based, for example, on the number of switch link inputs per node.

Abstract: A multi-stage network which achieves the same overall connectivity as known networks but where individual switching nodes have no input selectivity and no output selectivity. Each node is enabled or disabled to control communication therethrough in response to a single control signal. The functionality of a switching network is achieved by controlling which nodes are enabled rather than specifying connections of particular node inputs and outputs to be effected by the nodes. In a photonic network embodiment, each network node is implemented using a single symmetric self electro-optic effect device (S-SEED).

Abstract: A network comprising a plurality of successively interconnected node stages where each node has an associated data connection state and includes a control element, significantly implemented as part of the node itself, for controlling the data connection state of at least one node of the following stage. The network is well suited for optical implementation and is controlled by shifting bits into the network for storage by the control elements rather than relying on spatial light modulators.

Abstract: A network arrangement and control method where, before any transmission of data occurs for a particular communication, a network controller determines an unused path to provide a connection, advantageously all the way through the network from a given inlet to a given outlet. Once the identity of the unused path is known, the controller determines control information for use in activating that path and transmits that control information into the network, significantly via the network inlets. The network responds by activating the determined path and communication is enabled via the activated path, but only for the single connection and no buffering of information is required within the network. The network is particularly well suited for optical implementation and control is effected without the use of spatial light modulators but rather by means of control elements embedded within the network itself.

Abstract: A multi-stage network which achieves the same overall connectivity as known networks but where individual switching nodes have no input selectivity and no output selectivity. Each node is enabled or disabled to control communication therethrough in response to a single control signal. The functionality of a switching network is achieved by controlling which nodes are enabled rather than specifying connections of particular node inputs and outputs to be effected by the nodes. In a photonic network embodiment, each network node is implemented using a single symmetric self electro-optic effect device (S-SEED).

Abstract: A reduced-blocking system where a perfect shuffle equivalent network having a plurality of node stages successively interconnected by link stages, is advantageously combined with expansion before the node stages and/or concentration after the node stages in a manner allowing the design of a system with arbitrarily low or zero blocking probability. An illustrative photonic system implementation uses free-space optical apparatus to effect a low loss, crossover interconnection of two-dimensional arrays of switching nodes comprising, for example, symmetric self electro-optic effect devices (S-SEEDs). Several low loss beam conbination techniques are used to direct multiple arrays of beams to an S-SEED array, and to redirect a reflected output beam array to a subsequent node stage.

Abstract: A network control arrangement where path hunts through a first network are performed with reference to a second network that is topologically equivalent to the first. Path hunts through a crossover network, well-suited for implementation in the photonics domain, are performed with reference to a topologically equivalent shuffle network using a very efficient, shuffle network path hunt algorithm.

Abstract: A network control arrangement where two or more path hunt operations are performed in parallel using one or both of two techniques: (1) reading a memory for a second path hunt operation during the time that information read from the memory for a first path hunt operation is being processed to select a path, and (2) maintaining duplicate memories and reading from them both to perform two path hunt operations before either memory is updated. A disjoint path check unit rapidly determines whether all of the network paths from a first inlet to a first outlet are disjoint from all of the network paths from a second inlet to a second outlet. Plural path hunts are performed only when all network paths from the first inlet to the first outlet are determined to be disjoint from all network paths from the second inlet to the second outlet.

Abstract: A network control arrangement where stage-specific busy/idle information is stored using individual memories for each stage, and path hunting is effected by combining the busy/idle information for all stages concurrently rather than sequentially. A single binary number, comprising a concatenation of an inlet number, a path number and an outlet number, uniquely identifies a particular network path between a given inlet and outlet. The stage busy/idle information for the path components, e.g., network nodes or links, for all network path between the given inlet and outlet is stored at a single address of a stage memory. The memory address for a particular stage is a specified subset of the bits of the inlet and outlet numbers. The memories for all stages are read concurrently to simultaneously determine all idle paths and, after a path is selected, all stage memories are concurrently updated.

Abstract: A switching network where a large class of combinatorial designs which are well known in the mathematical literature are for the first time applied to advantageously define the pattern of permanent connections effected between network input channels and initial network crosspoints, illustratively by a connection arrangement of a two-stage, rearrangeable network. The class of combinatorial designs comprises designs of three types: (1) block designs, (2) orthogonal arrays, and (3) difference sets. Each of these is used in a unique manner to derive an advantageous pattern of permanent connections.

Abstract: A switching network where a large class of combinatorial designs which are well known in the mathematical literature are for the first time applied to advantageously define the pattern of permanent connections effected between network input channels and initial network corsspoints, illustratively by a connection arrangement of a two-stage, rearrangeable network. The class of combinatorial designs comprises designs of three types: (1) block designs, (2) orthogonal arrays, and (3) difference sets. Each of these is used in a unique manner to derive an advantageous pattern of permanent connections.