Abstract: An apparatus permits built-in self-test (“BIST”) of an IC that includes a memory element having more than one impermissible operation. A code generator accepts a clock signal and generates a test code in response to it. A decoder accepts the test code and generates at least two output lines to disable the impermissible operations during the test. When the decoder is in a decode disabled condition, the output lines reflect a value that permit all possible memory operations.

Abstract: A clock ratio data synchronizer is provided that utilizes a plurality of flip flops to synchronize data received by the synchronizer from first clock domain logic at a first clock frequency to a clock frequency of second clock domain logic. Each flip flop is capable of sampling data only on an edge of a clock and outputting data only on an edge of the clock. By utilizing flip flops in the synchronizer, data values are only allowed to change on clock edges. This, in turn, greatly improves clock skew tolerance, and also setup time margins for the first clock domain logic and for the second clock domain logic.

Abstract: A memory array test system and method provides for testing a memory array in a manufactured chip. In accordance with one aspect of the invention, a system includes memory test input logic that acquires test data via a data port, a memory test enable logic and a memory test output logic. In accordance with another aspect of the invention, a method acquires test data via a data port, writes the test data to a memory address in the memory array, and reads output data from the memory address in the memory array. Then, the method compares the test data and the output data to determine if the memory address in the memory array passes a test.

Abstract: An electronic circuit for enabling differential tests. In representative embodiments, the electronic circuit includes a first differential receiver having first and second inputs and an output, a first switch having first and second data inputs, a control input, and an output, and a first control device having an output. The first input of the first differential receiver is connected to a first contact and to a first single ended receiver input, and the second input of the first differential receiver is connected to a second contact and to a second single ended receiver input. The first data input of first switch is connected to first single ended receiver output, and the second data input of first switch is connected to first differential receiver output. The first control device output is connected to first switch control input.

Abstract: The present invention provides a synchronizer for receiving an incoming data signal of a first clock domain and for outputting a data signal of a second clock domain. The synchronizer comprises an input stage, a master latch, a transfer stage and a slave latch. The input stage receives the data signal of the first clock domain and outputs the data signal to the master latch when the input stage is clocked with a master clock signal. The master latch stores the data signal at a storage node of the master latch. The master latch has a resolve time associated with it during which the master latch seeks to resolve the data signal to a logic 0 or a logic 1. The transfer stage transfers the data signal stored in the master latch to the slave latch when the transfer stage is clocked with a slave clock signal.

Abstract: A method and system of identifying one or more nets in a digital IC design that are at risk of electromigration comprises selecting a manufacturing process for the digital IC design and obtaining a clock period and process voltage. A voltage waveform transition time and effective capacitance is calculated for one or more of the nets. A maximum allowable effective capacitance for each one of the nets is calculated based upon a peak current analysis or an RMS current analysis. The effective capacitance for each net is compared against the maximum allowable capacitance to identify those nets that are at risk of failure due to the effects of electromigration.

Abstract: A gating signal checker system and method are provided to perform clock gating check on a logic cell. In accordance with one aspect of the invention, the system includes logic that determines a clock transition time of a clock input into the logic cell, and logic that determines a transition time of at least one gating signal input into the logic cell. Also included in the gating signal checker system is logic that calculates a clock difference time between the clock transition time and the transition time of the at least one gating signal input into the logic cell, and logic that determines that the logic cell fails the clock gating check if the clock difference time is negative. In accordance with another aspect of the invention, a method performs a clock gating check on a logic cell by determining a clock transition time of a clock input into the logic cell, and determining a transition time of at least one gating signal input into the logic cell.

Abstract: An apparatus and method are provided for preventing buffers used to reduce delays on long lines of an IC from being damaged due to charge that collects on the buffers during manufacturing. In accordance with the present invention, a protection diode is included directly in at least each buffer that is used for this purpose, i.e., for the purpose of preventing delays on long lines of the IC. By including a protection diode in at least each buffer that is used for this purpose, the present invention obviates the need for having to use tools during the IC design process to determine a suitable location for a protection diode.

Abstract: Chip analyzer systems and methods are provided to partition chip designs into smaller blocks in order to test speed paths more efficiently for integrated circuits. In accordance with one aspect of the invention, a system includes a chip analyzer and an automatic test generator. The chip analyzer partitions information corresponding to the integrated circuit into a plurality of circuit configuration blocks, and creates a model of a selected circuit configuration block in the integrated circuit. The automatic test generator receives the model from the chip analyzer, and creates tests from the model to determine the correctness of the integrated circuit. In accordance with another aspect of the invention, the method partitions the integrated circuit into a plurality of circuit configurations, and selects a circuit configuration on the integrated circuit to be tested.

Abstract: For drivers of different sizes driving signal lines of different lengths, maximum transition time constraints are compared to signal transition times to determine whether a potential noise problem exists with respect to the signal lines. Each driver size has a maximum line length and a maximum transition time associated with it. These maximum transition time constraints are used to determine whether the signal lines connected to respective drivers in the IC will have potential noise problems associated with them. For each signal line in the IC design, the signal transition time is determined and compared to the maximum transition time constraint. If the signal transition time exceeds the maximum transition time constraint, a potential noise problem exists with respect to the signal line.

Abstract: A system for simplifying clock construction and distribution within an integrated circuit, and for simplifying analysis within the integrated circuit. The system utilizes a memory, software stored within said memory defining functions to be performed by the system, and a processor.

Abstract: A method and system of identifying one or more nets in a digital IC design that are at risk of electromigration comprises selecting a manufacturing process for the digital IC design and obtaining a clock period and process voltage. A voltage waveform transition time and effective capacitance is calculated for one or more of the nets. A maximum allowable effective capacitance for each one of the nets is calculated based upon a peak current analysis or an RMS current analysis. The effective capacitance for each net is compared against the maximum allowable capacitance to identify those nets that are at risk of failure due to the effects of electromigration.

Abstract: A gating signal checker system and method are provided to perform clock gating check on a logic cell. In accordance with one aspect of the invention, the system includes logic that determines a clock transition time of a clock input into the logic cell, and logic that determines a transition time of at least one gating signal input into the logic cell. Also included in the gating signal checker system is logic that calculates a clock difference time between the clock transition time and the transition time of the at least one gating signal input into the logic cell, and logic that determines that the logic cell fails the clock gating check if the clock difference time is negative. In accordance with another aspect of the invention, a method performs a clock gating check on a logic cell by determining a clock transition time of a clock input into the logic cell, and determining a transition time of at least one gating signal input into the logic cell.

Abstract: A memory array test system and method provides for testing a memory array in a manufactured chip. In accordance with one aspect of the invention, a system includes memory test input logic that acquires test data via a data port, a memory test enable logic and a memory test output logic. In accordance with another aspect of the invention, a method acquires test data via a data port, writes the test data to a memory address in the memory array, and reads output data from the memory address in the memory array. Then, the method compares the test data and the output data to determine if the memory address in the memory array passes a test.

Abstract: Chip analyzer systems and methods are provided to partition chip designs into smaller blocks in order to test speed paths more efficiently for integrated circuits. In accordance with one aspect of the invention, a system includes a chip analyzer and an automatic test generator. The chip analyzer partitions information corresponding to the integrated circuit into a plurality of circuit configuration blocks, and creates a model of a selected circuit configuration block in the integrated circuit. The automatic test generator receives the model from the chip analyzer, and creates tests from the model to determine the correctness of the integrated circuit. In accordance with another aspect of the invention, the method partitions the integrated circuit into a plurality of circuit configurations, and selects a circuit configuration on the integrated circuit to be tested.

Abstract: An electronic circuit for enabling differential tests. In representative embodiments, the electronic circuit includes a first differential receiver having first and second inputs and an output, a first switch having first and second data inputs, a control input, and an output, and a first control device having an output. The first input of the first differential receiver is connected to a first contact and to a first single ended receiver input, and the second input of the first differential receiver is connected to a second contact and to a second single ended receiver input. The first data input of first switch is connected to first single ended receiver output, and the second data input of first switch is connected to first differential receiver output. The first control device output is connected to first switch control input.

Abstract: A system for simplifying clock construction and distribution within an integrated circuit, and for simplifying analysis within the integrated circuit. The system utilizes a memory, software stored within said memory defining functions to be performed by the system, and a processor.

Abstract: A clock ratio data synchronizer is provided that utilizes a plurality of flip flops to synchronize data received by the synchronizer from first clock domain logic at a first clock frequency to a clock frequency of second clock domain logic. Each flip flop is capable of sampling data only on an edge of a clock and outputting data only on an edge of the clock. By utilizing flip flops in the synchronizer, data values are only allowed to change on clock edges. This, in turn, greatly improves clock skew tolerance, and also setup time margins for the first clock domain logic and for the second clock domain logic.

Abstract: For drivers of different sizes driving signal lines of different lengths, maximum transition time constraints are compared to signal transition times to determine whether a potential noise problem exists with respect to the signal lines. Each driver size has a maximum line length and a maximum transition time associated with it. These maximum transition time constraints are used to determine whether the signal lines connected to respective drivers in the IC will have potential noise problems associated with them. For each signal line in the IC design, the signal transition time is determined and compared to the maximum transition time constraint. If the signal transition time exceeds the maximum transition time constraint, a potential noise problem exists with respect to the signal line.

Abstract: An apparatus permits built-in self-test (“BIST”) of an IC that includes a memory element 104 having one or more impermissible operations. A code generator 401 accepts a clock signal 218 and generates a test code in response to it. A decoder 402 accepts the test code and generates at least two output lines 318, 319, 320, 321 where when in a decode enabled condition, the output lines 318, 319, 320, 321 are responsive to the test code and reflect a value that is combined with respective memory access lines comprising first and second write address outputs 309, 310 and first and second read address outputs 311, 312 as well as enable bits from first and second write enable registers 210, 211 and first and second read enable registers 214, 215 to disable the one or more impermissible operations. When the decoder 402 is in a decode disabled condition, the output lines 318, 319, 320, 321 reflect a value that when combined with the respective memory access lines enables all possible memory operations.