Abstract: The disclosure provides a method including: identifying a fill-dense region of an integrated circuit (IC) layout having a plurality of fill cells, and a target fill region of the IC layout adjacent to the fill-dense region and free of fill cells; modifying the IC layout by removing a fill cell from the fill-dense region and inserting a duplicate of the removed fill cell within the target fill region to at least partially fill the target fill region; and providing instructions to manufacture an IC using the modified IC layout. The method may reduce a feature density of the fill-dense region to less than an allowable feature density, while adding fill features to otherwise unfillable regions.

Abstract: Methods according to the disclosure identify at least one corner violation including a pair of fill cells of the fill region having a corner-to-corner shape profile that violates a manufacturing specification for the fill region of the IC layout; creating an exclusion layer for the at least one corner violation of the IC layout; removing the at least one corner violation from the fill region using the exclusion layer to form a modified IC layout, wherein at least a portion of each of the pair of fill cells remains in the modified IC layout after removing the at least one corner violation; and manufacturing the modified IC layout to include a fill shape based on the fill region after removing the at least one corner violation, the fill shape being compliant with the manufacturing specification for the fill region of the IC layout.

Abstract: The disclosure provides a method including: identifying a fill-dense region of an integrated circuit (IC) layout having a plurality of fill cells, and a target fill region of the IC layout adjacent to the fill-dense region and free of fill cells; modifying the IC layout by removing a fill cell from the fill-dense region and inserting a duplicate of the removed fill cell within the target fill region to at least partially fill the target fill region; and providing instructions to manufacture an IC using the modified IC layout. The method may reduce a feature density of the fill-dense region to less than an allowable feature density, while adding fill features to otherwise unfillable regions.

Abstract: Methods according to the disclosure identify at least one corner violation including a pair of fill cells of the fill region having a corner-to-corner shape profile that violates a manufacturing specification for the fill region of the IC layout; creating an exclusion layer for the at least one corner violation of the IC layout; removing the at least one corner violation from the fill region using the exclusion layer to form a modified IC layout, wherein at least a portion of each of the pair of fill cells remains in the modified IC layout after removing the at least one corner violation; and manufacturing the modified IC layout to include a fill shape based on the fill region after removing the at least one corner violation, the fill shape being compliant with the manufacturing specification for the fill region of the IC layout.