Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series.

Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package.

Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series.

Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package.

Abstract: Apparatus and method for producing memory modules having a plurality of branches connected to a memory bus, each branch containing at least one dynamic random access memory (DRAM) device or SDRAM device connected to the memory bus via at least one transmission signal (TS) line and/or at least one sub-transmission signal (STS) line. The memory modules include at least one branch containing a capacitor connected in parallel to the TS line or STS line and the DRAM device or SDRAM device. A computing system implementing the memory modules is also discussed.

Abstract: Apparatus and method for producing memory modules having a plurality of dynamic random access memory (DRAM) devices or synchronous random access memory (SDRAM) devices connected to a memory bus, each DRAM or SDRAM device connected to the memory bus via a transmission signal (TS) line. The memory bus includes at least one TS line having a capacitor connected to the TS line in parallel to the plurality of DRAM or SDRAM devices, the TS line connected to the memory bus between a signal insertion end and an attachment point of a TS line of a first DRAM or SDRAM device. A computing system implementing the memory modules is also discussed.

Abstract: Apparatus and method for producing memory modules having a plurality of dynamic random access memory (DRAM) devices or synchronous random access memory (SDRAM) devices connected to a memory bus, each DRAM or SDRAM device connected to the memory bus via a transmission signal (TS) line. The memory bus includes at least one TS line having a capacitor connected to the TS line in parallel to the plurality of DRAM or SDRAM devices, the TS line connected to the memory bus between a signal insertion end and an attachment point of a TS line of a first DRAM or SDRAM device. A computing system implementing the memory modules is also discussed.

Abstract: Apparatus and method for producing memory modules having a plurality of branches connected to a memory bus, each branch containing at least one dynamic random access memory (DRAM) device or SDRAM device connected to the memory bus via at least one transmission signal (TS) line and/or at least one sub-transmission signal (STS) line. The memory modules include at least one branch containing a capacitor connected in parallel to the TS line or STS line and the DRAM device or SDRAM device. A computing system implementing the memory modules is also discussed.

Abstract: Apparatus and method for producing memory modules having a plurality of branches connected to a memory bus, each branch containing at least one dynamic random access memory (DRAM) device or synchronous random access memory (SDRAM) device connected to the memory bus via at least one transmission signal (TS) line and/or at least one sub-transmission signal (STS) line. The memory modules include at least one branch containing a resistor connected to the TS line or STS line and connected series with the DRAM device or SDRAM device and connected to the memory bus. A computing system implementing the memory modules is also discussed.