Abstract: A fixed-size data packet switch comprising: 1) N input ports for receiving incoming fixed-size data packets at a first data rate and outputting the fixed-size data packets at the first data rate; 2) N output ports for receiving fixed-size data packets at the first data rate and outputting the fixed-size data packets at the first data rate; and 3) a switch fabric interconnecting the N input ports and the N output ports.

Abstract: A packet switch capable of receiving fixed size data cells from N input ports and transmitting the fixed size data cells to N output ports. The packet switch comprises: 1) a frame deserializer for receiving the data cells as serial bits from the N input ports and transmitting the data cells as parallel bits in data frames containing a plurality of data cells, wherein each of the plurality of data cells in each data frame are destined for a common output port; 2) a frame serializer for receiving the data frames and transmitting the plurality of data cells in the data frames as serial bits to the N output ports; and 3) a shared buffer coupling the frame deserializer and the frame serializer for receiving and buffering the data frames from the frame deserializer and transmitting the buffered data frames to the frame serializer.

Abstract: A packet switch for switching cells comprising fixed-size data packets.

Abstract: A method and circuit buffer for temporarily holding packets of information. The buffer may include a first memory and a second memory for holding the packets of information. The first memory may be a read-once memory in which data stored in the first memory is destroyed upon being read therefrom the first time. The second memory may be a memory in which stored data therein is not destroyed following the data being read from the second memory the first time. The buffer includes at least one queue. The head-of-line packet of the at least one queue is stored in the second memory. Incoming fanout splitting packets are stored in the second memory and other incoming packets are initially stored in the first memory.

Abstract: A method and circuit are disclosed for a buffer for temporarily holding packets of information. The buffer may include a first memory and a second memory for holding the packets of information. The first memory may be a read-once memory in which data stored in the first memory is destroyed upon being read therefrom the first time. The second memory may be a memory in which stored data therein is not destroyed following the data being read from the second memory the first time. The buffer includes at least one queue. The head-of-line packet of the at least one queue is stored in the second memory. Incoming fanout splitting packets are stored in the second memory and other incoming packets are initially stored in the first memory.

Abstract: A packet switch capable of receiving fixed size data cells from N input ports and transmitting the fixed size data cells to N output ports. The packet switch comprises: 1) a frame deserializer for receiving the data cells as serial bits from the N input ports and transmitting the data cells as parallel bits in data frames containing a plurality of data cells, wherein each of the plurality of data cells in each data frame are destined for a common output port; 2) a frame serializer for receiving the data frames and transmitting the plurality of data cells in the data frames as serial bits to the N output ports; and 3) a shared buffer coupling the frame deserializer and the frame serializer for receiving and buffering the data frames from the frame deserializer and transmitting the buffered data frames to the frame serializer.

Abstract: A packet switch for switching cells comprising fixed-size data packets.

Abstract: A fixed-size data packet switch comprising: 1) N input ports for receiving incoming fixed-size data packets at a first data rate and outputting the fixed-size data packets at the first data rate; 2) N output ports for receiving fixed-size data packets at the first data rate and outputting the fixed-size data packets at the first data rate; and 3) a switch fabric interconnecting the N input ports and the N output ports.