Abstract: A method and arrangement for shutting off a receive channel in a data communications system to prevent accidental or intentional overwhelming of the memory of the system such as that caused by a continuous burst of short frame data. The data frames received are monitored by a shutoff counter as they are received on one of the channels of a serial input/output (I/O) device. When the shutoff count is reached, the receive channel will be shut off. The current value of the shutoff counter is compared to a value stored in a warning register. Before reaching the shutoff count, a warning is generated when the current shutoff counter value reaches the warning register value.

Abstract: A method and arrangement for performing direct memory access in a computer system having multi-channel direct memory access (DMA) is provided with a host computer having a main memory and a processor that runs software, a system interface bus coupling the host computer and the main memory, and multiple DMA controllers, on separate chips, coupled to the system interface bus. These multiple DMA controllers provide the system with multiple input/output (I/O) channels. A common buffer pool having a plurality of buffers is accessible to each of the multiple channels for buffering data transferred to or from the host computer. A status queue is also provided, with each entry in the status queue indicating whether a corresponding buffer from the common pool of buffers is a free buffer available for use by one of the DMA channels in a DMA transaction.

Abstract: This invention provides efficient and flexible data transfer management for a First-In First-Out (FIFO) buffer connects to a system bus and implements multiple data thresholds (e.g., two). Data transfer by the FIFO is controlled by either casually or more aggressively acquiring the system bus based on the amount of data inside the FIFO and on the state of the system bus. By balancing the bus activity level against the FIFO data level, bus access is facilitated at times when the bus has lower activity. This makes the FIFO less obtrusive when moving data across the bus. As a result, the bus is used more efficiently. The system bus is casually acquired when the FIFO data level reaches a soft threshold and the system bus is idle. Casual control of the system bus is relinquished when request from another device sharing the bus is received and a predetermined amount of data has been transferred. On the other hand, the system bus is more aggressively acquired when the FIFO data level reaches a hard threshold.