Abstract: The present invention relates to a system according to claim 1, where the pixel buffer cache comprises at least one row descriptor for tracking and monitoring the activities of read and write requests of a particular tile. A system for providing a high bandwidth memory access to a graphics processor comprising: (a) a frame buffer for storing at least one frame, where said frame is stored in a tiled manner; (b) a memory controller for controlling said frame buffer; (c) a pixel buffer cache for storing multiple sections of at least one memory row of said frame buffer, and for processing requests to access pixels of said frame buffer; (d) a graphics accelerator having an interface to said pixel buffer cache for processing a group of related pixels; and (e) a CPU for processing graphic commands and controlling said graphics accelerator and said pixel buffer cache.

Abstract: The present invention relates to a system for the parallel processing of a number of binstream bins comprising: (a) inputs for receiving the codIOffset, the codIRange and the bitstream suffix bits; (b) a first circuit for the parallel processing of said number of said bitstream suffix bits, said codIOffset, and said codIRange for producing an indication of the binstream suffix length magnitude; (c) a second circuit for the parallel processing of said number of said bitstream suffix bits, said codIOffset, and said codIRange for producing said number of speculative codIOffsets; (d) a third circuit for combining the products of said first circuit and the products of said second circuit for producing a new codIOffset; and (e) a fourth circuit for combining the products of said first circuit with said number of constants for producing a number indicative of the binstream suffix length.

Abstract: Apparatus for processing audio signal streams including a plurality of audio signal inputs, an audio signal output, and a plurality of audio signal processing units, wherein the audio signal input, the audio signal output, and the plurality of audio signal processing units are connected to and controlled by a Micro Controller Unit (MCU), and wherein the audio signal processing units are configured to process more than one audio signal stream at the same time. Related apparatus and methods are also described.

Abstract: A cache memory device for location between a main memory and a requesting processor is disclosed. The main memory stores memory blocks, some of which are temporarily located in the cache memory device to improve retrieval performance. The cache memory device is configured to receive requests for respective memory blocks, and the cache memory device comprises an input pooling unit for pooling incoming requests for blocks of memory as well as a request selection mechanism configured for selecting amongst those pooled requests. The request selection mechanism operates according to one or more optimization criteria to optimize the operation of the cache memory device. The device is particularly useful for image and video compression.

Abstract: A method for estimating image-to-image motion of a pixel block in a stream of images which includes a current image which includes the pixel block and a reference image, the method including performing a hierarchical search in a search area of the reference image, including producing a decimated reference image and a decimated pixel block, searching for a location in the search area of the decimated reference image which best fits the decimated pixel block, repeating the producing and the searching for more than one level of hierarchy, determining a first candidate location in the reference image which corresponds to the best fitting location, determining a second candidate location in the reference image by a method other than the hierarchical search, performing a search in the reference image for refined locations of the first and the second candidate locations, selecting one final location from the refined candidate locations, and using the final location for estimating the motion.

Abstract: An integrated circuit for processing a media stream, including an RF input interface, an RF receiver unit configured for receiving an RF media stream from the RF input interface and extracting the media stream from the RF media stream, an input interface unit configured for receiving the media stream from a content source, a plurality of processing units, a switch, operatively connected to the RF receiver unit, to the input interface unit, and to each of the processing units, the switch configured to allow more than one of the operatively connected units to simultaneously receive the media stream, thereby allowing simultaneous processing of the media stream by the processing units, and an output interface, operatively connected to the switch, configured for outputting the simultaneously processed media stream. Related apparatus and methods are also described.

Abstract: Apparatus for performing multiplexing and de-multiplexing of packetized digital data streams, including receivers for receiving data packets from packetized digital data streams, validating the packets, and transmitting only valid packets, PID filters for filtering packets according to a Packet ID included in the packets, the filters receiving valid packets from the receivers, and associating a store-or-drop value with each valid packet, input FIFO buffers for receiving valid packets from the receivers, receiving the store-or-drop value from the PID filters, and storing data based, at least in part, on the store-or-drop value, an input/output unit for transmitting the stored data from the input FIFO buffers to an external memory and reading data from the external memory, output FIFO buffers for receiving data from the input/output unit and storing the data, and transmitters for reading digital data packets from the output FIFO buffers and transmitting the packets as a packetized digital data stream, thereby d

Abstract: Video format transformation apparatus including a field/frame assessment module, for associating a field/frame value with a specific pixel. A first value is associated with the specific pixel based on a first function of a group of pixels in proximity to the specific pixel, the group of pixels being in a video frame which includes the specific pixel. A second value is associated with the specific pixel based on a first result and a second result. The first result is of a second function of a second group of pixels, including pixels of an even parity video field within the video frame. The second result is of the second function of a third group of pixels, including pixels of an odd parity video field within the video frame. The field/frame value is associated with the specific pixel based on a third function of the first value and the second value.

Abstract: A home gateway for a home media network. The home gateway comprises a number of input interfaces each configured for receiving encrypted & unencrypted data from a content source, a layout generation unit adapted to generate substantially simultaneously a number of different composite layout streams. Each one of the different composite layout streams is generated according to one or more of the number of input interfaces. The home gateway further comprises a number of output interfaces for providing a number of client stations with the ability to access one or more of the number of different composite layout streams in encrypted & unencrypted manner.

Abstract: An integrated circuit for pre-processing, encoding, decoding, transcoding, indexing, blending, post-processing and display of media streams, in accordance with a variety of compression algorithms, DRM schemes and related industry standards and recommendations such as OCAP, ISMA, DLNA, MPAA etc. The integrated circuit comprises an input interface configured for receiving the media streams from content sources, a plurality of processing units, system CPU, and sophisticated switch and memory controller, electronically connected to the input interface and directly connected to each one of the processing units. The integrated circuit further comprises an output interface that is operatively connected to the switch and configured for outputting the simultaneously processed media streams.