Abstract: Pulsed current circuitry for electromigration testing of semiconductor integrated circuits and components. The circuit includes a multiplexer that outputs analog voltage pulses, and is capable of generating both bipolar and unipolar voltage pulses. At least one operational amplifier and resistor receive the voltage pulses from the multiplexer and convert the voltage pulses to current pulses. A charge booster circuit is provided for minimizing overshoots and undershoots during transitions between current levels in the test circuit.

Abstract: Pulsed current circuitry for electromigration testing of semiconductor integrated circuits and components. The circuit includes a multiplexer that outputs analog voltage pulses, and is capable of generating both bipolar and unipolar voltage pulses. At least one operational amplifier and resistor receive the voltage pulses from the multiplexer and convert the voltage pulses to current pulses. A charge booster circuit is provided for minimizing overshoots and undershoots during transitions between current levels in the test circuit.

Abstract: In accordance with an aspect, a thermally-controllable integrated unit is configured to hold devices under test. The integrated unit includes at least one heater board, comprised of a thermally-conductive material and provided with at least one global heater configured to globally heat the DUT board. A DUT board of the integrated unit includes a DUT board in thermal contact with the at least one heater board, the DUT board including a plurality of sockets, each socket configured to hold at least one DUT. The DUT has conductor paths to conduct electrical signals between test equipment and the terminals of DUTs in the sockets. Each socket includes an associated temperature sensor and a separately controllable local heater configured to, based on a temperature indication from the temperature sensor, heat a DUT in that socket.

Abstract: In accordance with an aspect, a thermally-controllable integrated unit is configured to hold devices under test. The integrated unit includes at least one heater board, comprised of a thermally-conductive material and provided with at least one global heater configured to globally heat the DUT board. A DUT board of the integrated unit includes a DUT board in thermal contact with the at least one heater board, the DUT board including a plurality of sockets, each socket configured to hold at least one DUT. The DUT has conductor paths to conduct electrical signals between test equipment and the terminals of DUTs in the sockets. Each socket includes an associated temperature sensor and a separately controllable local heater configured to, based on a temperature indication from the temperature sensor, heat a DUT in that socket.

Abstract: In an electrical circuit for testing electrical current using a plurality of precision resistors connected in parallel or in series, a range finder for receiving the current to be measured with the voltage drop across the range finder being indicative of a current sub-range for measurement. In a preferred embodiment, a range finder has a first bipolar transistor and a second bipolar transistor connected in parallel and in opposite polarity with the emitter and base of each transistor connected together whereby each transistor functions as an emitter-base diode.

Abstract: A pulsed current generator circuit for providing current pulses to a device under test includes a current source for applying a current to the device under test and a controlled current shunt for shunting current from the device under test. A booster circuit is provided for supplying a booster current to the device under test when the controlled current shunt is opened and current again flows through the device under test, thereby facilitating recharge of a parasitic capacitance associated with the device under test.

Abstract: In an electrical for testing electrical current using a plurality of precision resistors connected in parallel or in series, a range finder for receiving the current to be measured with the voltage drop across the range finder being indicative of a current sub-range for measurement. In a preferred embodiment, a range finder comprises a first bipolar transistor and a second bipolar transistor connected in parallel and in opposite polarity with the emitter and base of each transistor connected together whereby each transistor functions as an emitter-base diode.

Abstract: A pulsed current generator circuit for providing current pulses to a device under test includes a current source for applying a current to the device under test and a controlled current shunt for shunting current from the device under test. A booster circuit is provided for supplying a booster current to the device under test when the controlled current shunt is opened and current again flows through the device under test, thereby facilitating recharge of a parasitic capacitance associated with the device under test.

Abstract: A test circuit for applying bipolar current pulse to first and second terminals of device under test (DUT) includes a first DC current source and a first switch having a first common terminal, a second DC current source and a second switch having a second common terminal, and means for connecting a device under test between the first and second common terminals. A timing generator selectively controls conduction of the first switch and the second switch whereby when the first switch is closed the current from the second DC current source flows through the device under test and the first switch to a circuit ground, and when the second switch is closed the current from the first DC current course flows through the device under test and the second switch to a circuit ground. Pulse repetition rate and duty cycle of the current pulses are controlled by the control voltage pulses from the timing generator.

Abstract: A technique for providing electrostatic discharge (ESD) protection for an open-drain CMOS I/O buffer circuit. having an output terminal. An NMOS enhancement-mode transistor has its drain connected to the VDD power bus for the buffer circuit, its source connected to the output terminal, and its gate connected to a noise-free internal VSS power bus (VSSI). The bulk region is connected to the VSS power bus (VSSE) for the I/O buffer circuit. ESD protection is provided by a parasitic lateral npn bipolar transistor that is inherent to the NMOS transistor. The parasitic lateral npn bipolar transistor has an emitter formed from the drain-to-bulk junction of the NMOS transistor, a collector formed from the source-to-bulk junction of the NMOS transistor, and a base formed in the bulk region.