Patents by Inventor Geeta K. Desai

Geeta K. Desai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low power memory controller with leaded double data rate DRAM package on a two layer printed circuit board
    Patent number: 7657774
    Abstract: An integrated circuit is provided that includes an execution engine and a memory controller. The execution engine is clocked at a first rate and the memory controller is clocked at a second rate that is less than the first rate. Pins on the integrated circuit can transfer data to and from the integrated circuit on both the rising and falling edges of a second clock transitioning at the second clock rate. The integrated circuit is preferably packaged using a lead frame and wire bonds extending from pads on the integrated circuit to corresponding leads. The leads are secured to trace conductors on a surface of a printed circuit board. The board contains no more than two conductive layers separated by a dielectric layer.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: February 2, 2010
    Assignee: LSI Logic Corporation
    Inventors: Eric Hung, Geeta K. Desai, Vijendra Kuroodi, Alexander Miretsky, Mirko Vojnovic
  • Low power memory controller with leaded double data rate DRAM package arranged on a two layer printed circuit board
    Patent number: 7409572
    Abstract: An integrated circuit is provided that includes an execution engine and a memory controller. The execution engine is clocked at a first rate and the memory controller is clocked at a second rate that is less than the first rate. Pins on the integrated circuit can transfer data to and from the integrated circuit on both the rising and falling edges of a second clock transitioning at the second clock rate. The integrated circuit is preferably packaged using a lead frame and wire bonds extending from pads on the integrated circuit to corresponding leads. The leads are secured to trace conductors on a surface of a printed circuit board. The board contains no more than two conductive layers separated by a dielectric layer.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: August 5, 2008
    Assignee: LSI Corporation
    Inventors: Eric Hung, Geeta K. Desai, Vijendra Kuroodi, Alexander Miretsky, Mirko Vojnovic