Patents by Inventor Geetani R. Edirisooriya
Geetani R. Edirisooriya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230185747Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller’s performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: ApplicationFiled: February 8, 2023Publication date: June 15, 2023Inventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen
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Patent number: 11604746Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: GrantFiled: July 22, 2020Date of Patent: March 14, 2023Assignee: SK hynix NAND Product Solutions Corp.Inventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen
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Patent number: 11449446Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: GrantFiled: July 22, 2020Date of Patent: September 20, 2022Assignee: Intel CorporationInventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen
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Patent number: 10990546Abstract: A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access (DMA) data transfers by the first VM, a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the first primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM, and a direct memory access (DMA) descriptor processing circuit to process, using a working queue associated with the first primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM, and execute, using the first interface device, the DMA data transfer based on the access permission.Type: GrantFiled: February 19, 2019Date of Patent: April 27, 2021Assignee: Intel CorporationInventors: Samantha J. Edirisooriya, Geetani R. Edirisooriya, Roger C. Jeppsen, Pankaj Kumar
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Publication number: 20200349100Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: ApplicationFiled: July 22, 2020Publication date: November 5, 2020Inventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen
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Publication number: 20190179786Abstract: A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access (DMA) data transfers by the first VM, a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the first primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM, and a direct memory access (DMA) descriptor processing circuit to process, using a working queue associated with the first primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM, and execute, using the first interface device, the DMA data transfer based on the access permission.Type: ApplicationFiled: February 19, 2019Publication date: June 13, 2019Inventors: Samantha J. Edirisooriya, Geetani R. Edirisooriya, Roger C. Jeppsen, Pankaj Kumar
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Patent number: 10241947Abstract: A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access (DMA) data transfers by the first VM, a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the first primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM, and a direct memory access (DMA) descriptor processing circuit to process, using a working queue associated with the first primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM, and execute, using the first interface device, the DMA data transfer based on the access permission.Type: GrantFiled: February 3, 2017Date of Patent: March 26, 2019Assignee: Intel CorporationInventors: Samantha J. Edirisooriya, Geetani R. Edirisooriya, Roger C. Jeppsen, Pankaj Kumar
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Patent number: 10235302Abstract: In an embodiment, a processor for invalidating cache entries comprises: at least one processing unit; a processor cache; and direct cache unit. The direct cache unit is to receive, from a first device, a direct read request for data in a first cache entry in the processor cache; determine whether the direct read request is an invalidating read request; in response to a determination that the direct read request is an invalidating read request: send the data in the first cache entry directly from the processor cache to the first device without accessing a main memory; and invalidate the first cache entry in the processor cache. Other embodiments are described and claimed.Type: GrantFiled: December 12, 2016Date of Patent: March 19, 2019Assignee: Intel CorporationInventors: Samantha J. Edirisooriya, Geetani R. Edirisooriya
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Publication number: 20180225237Abstract: A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access (DMA) data transfers by the first VM, a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the first primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM, and a direct memory access (DMA) descriptor processing circuit to process, using a working queue associated with the first primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM, and execute, using the first interface device, the DMA data transfer based on the access permission.Type: ApplicationFiled: February 3, 2017Publication date: August 9, 2018Inventors: Samantha J. Edirisooriya, Geetani R. Edirisooriya, Roger C. Jeppsen, Pankaj Kumar
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Publication number: 20180165222Abstract: In an embodiment, a processor for invalidating cache entries comprises: at least one processing unit; a processor cache; and direct cache unit. The direct cache unit is to receive, from a first device, a direct read request for data in a first cache entry in the processor cache; determine whether the direct read request is an invalidating read request; in response to a determination that the direct read request is an invalidating read request: send the data in the first cache entry directly from the processor cache to the first device without accessing a main memory; and invalidate the first cache entry in the processor cache. Other embodiments are described and claimed.Type: ApplicationFiled: December 12, 2016Publication date: June 14, 2018Inventors: SAMANTHA J. EDIRISOORIYA, GEETANI R. EDIRISOORIYA
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Patent number: 9602237Abstract: An inbound sideband interface is provided to receive a message over a first sideband link, and parity logic is provided to calculate a parity bit for the message. Further, an outbound sideband interface is provided to forward the message to another device over a second sideband link. The second sideband link includes a plurality of data wires and a parity bit wire. The message is forwarded over at least some of the data wires and the parity bit is sent to the other device over the parity bit wire to correspond with the message.Type: GrantFiled: December 19, 2014Date of Patent: March 21, 2017Assignee: Intel CorporationInventors: Robert P. Adler, Geetani R. Edirisooriya, Joseph Murray, Deep K. Buch
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Publication number: 20160335208Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: ApplicationFiled: July 29, 2016Publication date: November 17, 2016Inventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen
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Patent number: 9417821Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: GrantFiled: September 30, 2011Date of Patent: August 16, 2016Assignee: Intel CorporationInventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen
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Publication number: 20160182186Abstract: An inbound sideband interface is provided to receive a message over a first sideband link, and parity logic is provided to calculate a parity bit for the message. Further, an outbound sideband interface is provided to forward the message to another device over a second sideband link. The second sideband link includes a plurality of data wires and a parity bit wire. The message is forwarded over at least some of the data wires and the parity bit is sent to the other device over the parity bit wire to correspond with the message.Type: ApplicationFiled: December 19, 2014Publication date: June 23, 2016Inventors: Robert P. Adler, Geetani R. Edirisooriya, Joseph Murray, Deep K. Buch
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Publication number: 20140189212Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.Type: ApplicationFiled: September 30, 2011Publication date: July 3, 2014Inventors: Thomas M. Slaight, Sivakumar Radhakrishnan, Mark Schmisseur, Pankaj Kumar, Saptarshi Mondal, Sin S. Tan, David C. Lee, Marc T. Jones, Geetani R. Edirisooriya, Bradley A. Burres, Brian M. Leitner, Kenneth C. Haren, Michael T. Klinglesmith, Matthew R. Wilcox, Eric J. Dahlen
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Patent number: 7596638Abstract: A method, apparatus, and system are disclosed. In one embodiment the method detects a temperature event in a processor and then modifies the bus frequency of an I/O bus coupled to an I/O controller hub in response to the temperature event. In another embodiment, the apparatus includes a temperature detection unit that detects a temperature event in a processor and, additionally, a bus frequency modification unit that will modify the bus frequency of an I/O bus in response to the temperature event.Type: GrantFiled: June 21, 2004Date of Patent: September 29, 2009Assignee: Intel CorporationInventors: John P. Lee, Aniruddha P. Joshi, Geetani R. Edirisooriya
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Patent number: 7376782Abstract: A computer system provides a program access to a first register during real mode operation by using an index register and a data register, wherein the index register and the data register are located in real mode memory space and the first register is located outside of real mode memory space.Type: GrantFiled: June 29, 2005Date of Patent: May 20, 2008Assignee: Intel CorporationInventors: Jasper Balraj, Geetani R. Edirisooriya, John P. Lee, Robert Strong, Jeffrey L. Rabe, Amber Huffman, Daniel Nemiroff, Rajeev Nalawadi
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Patent number: 7251755Abstract: In some embodiments, a method and apparatus for maintaining data integrity following parity error detection are described. In one embodiment, the method includes the blockage of bus transactions in response to detection of a parity error. Once bus transactions are suspended, a parity error handler routine is invoked to perform parity error recovery according to stored transaction information regarding an error bus transaction of the detected parity error. In one embodiment, the stored information includes a bus master that caused the error, as well as an address associated with the corrupt data for which the parity error was asserted. In one embodiment, data logging is performed to track the bus masters associated with error bus transactions to enable identification of problematic or old hardware devices. Other embodiments are described and claims.Type: GrantFiled: February 13, 2004Date of Patent: July 31, 2007Assignee: Intel CorporationInventors: Aniruddha P. Joshi, John P. Lee, Geetani R. Edirisooriya
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Patent number: 7213094Abstract: Method and apparatus for supporting multi-function PCI devices in PCI bridges. Respective pre-fetch buffers are allocated in response to respective initial data transfer requests issued by a multi-function PCI device. A programmable buffer fill watermark is set up for each pre-fetch buffer. While a portion of data corresponding to the data transfer requests fill the pre-fetch buffers, the fill level of each buffer is monitored to determine if it meets or exceeds its buffer fill watermark. In response to such a condition, the multi-function PCI device is connected to the PCI bridge and a virtual buffer is mapped to the pre-fetch buffer. The pre-fetch buffer is then emptied. During subsequent data transfers, each of the pre-fetch buffer becomes filled, the PCI device is connected, and the virtual buffer is mapped to the filled buffer. The process is continued until all data corresponding to the original data transfer request is received by the multi-function PCI device.Type: GrantFiled: February 17, 2004Date of Patent: May 1, 2007Assignee: Intel CorporationInventors: Geetani R. Edirisooriya, Aniruddha P. Joshi, John P. Lee