Patents by Inventor Geethakrishnan Narasimhan

Geethakrishnan Narasimhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7981800
    Abstract: A shallow trench isolation (STI) structure and method for forming the same is provided that reduces defects in a nitride film used as a field oxide mask and variations in pad oxide thickness. Generally, the method involves depositing a nitride over pad oxide on a substrate using plasma enhanced chemical vapor deposition (PECVD), and patterning the PECVD nitride to form a field oxide mask. In certain embodiments, patterning the PECVD nitride involves: (i) forming a patterned resist layer on the PECVD nitride; (ii) etching in a process chamber at least one opening through at least the PECVD nitride; and (iii) stripping the patterned resist layer in-situ in the same process chamber in which the at least one opening was etched through the PECVD nitride using a fluorine based plasma. Other embodiments are also disclosed.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: July 19, 2011
    Assignee: Cypress Semiconductor Corporation
    Inventors: Geethakrishnan Narasimhan, Mehran Sedigh
  • Patent number: 7425489
    Abstract: A method of making a semiconductor structure includes etching an isolation oxide. The isolation oxide is in a substrate, a gate layer is on the substrate, a patterned metallic layer is on the gate layer, and a first patterned etch-stop layer is on the metallic layer.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: September 16, 2008
    Assignee: Cypress Semiconductor Corporation
    Inventors: Geethakrishnan Narasimhan, Saurabh D. Chowdhury
  • Publication number: 20070210339
    Abstract: In one embodiment, a shared contact structure electrically connects a gate, a diffusion region, and another diffusion region. The shared contact structure may comprise a trench that exposes the gate, the diffusion region, and the other diffusion region. The trench may be filled with a metal to form electrical connections. The trench may be formed in a dielectric layer using a self-aligned etch step, for example.
    Type: Application
    Filed: March 9, 2006
    Publication date: September 13, 2007
    Inventors: Geethakrishnan Narasimhan, Bartosz Banachowicz, Ravindra Kapre