Abstract: Methods of scaling the thickness of the interfacial layer in electronic devices, such as NMOS transistors and PMOS transistors are described. Some embodiments provide a metal film or a metal nitride film that reduces the thickness of the interfacial layer by scavenging unbound oxygen from the interfacial layer (e.g., silicon oxide (SiOx)) and the high-? dielectric layer (e.g., hafnium oxide (HfOx)). Some embodiments advantageously include annealing the semiconductor substrate to promote or accelerate the scavenging.

Abstract: The enclosed disclosure relates to a method and apparatus for depositing functionalized nanoparticles within a semiconductor structure in order to create a nano-layer capable of enhancing imaging and contrast, The semiconductor structure can include any type of VNAND structure or 3D structure, The nanoparticles are formed in high-aspect ratio trenches of the structure and form a nano-layer. The functionalized nanoparticles comprise synthesized nanoparticles as well as organic molecules. The organic molecules are chosen to selectively bind to certain nanoparticles and surface materials.

Abstract: Methods for depositing metal films using a metal halide and metal organic precursors are described. The substrate is exposed to a first metal precursor and a second metal precursor to form the metal film. The exposures can be sequential or simultaneous. The metal films are relatively pure with a low carbon content.

Abstract: Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multi-Vt), and have improved device performance and reliability. The method comprises forming a P-dipole stack and an N-dipole stack on a semiconductor substrate by: depositing an interfacial layer (e.g., silicon oxide (SiOx)) on the top surface of the channel; depositing a hafnium-containing layer comprising hafnium oxide (HfOx) and having a thickness of less than or equal to 5 ? on the interfacial layer; and depositing a dipole layer comprising lanthanum nitride (LaN) on the hafnium-containing layer.

Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, an interfacial layer on a top surface of the channel, a high-? dielectric layer on the interfacial layer, a dipole layer on the high-? dielectric layer, and a capping layer on the dipole layer. In some embodiments, the dipole layer comprises a metal oxynitride (MON), such as aluminum oxynitride (AlON). In some embodiments, the methods comprise annealing the substrate to drive atoms from the dipole layer into one or more of the interfacial layer or the high-? dielectric layer.

Abstract: Methods of depositing a metal film by exposing a substrate surface to a halide precursor and an organosilane reactant are described. The halide precursor comprises a compound of general formula (I): MQzRm, wherein M is a metal, Q is a halogen selected from Cl, Br, F or I, z is from 1 to 6, R is selected from alkyl, CO, and cyclopentadienyl, and m is from 0 to 6. The aluminum reactant comprises a compound of general formula (II) or general formula (III): wherein R1, R2, R3, R4, R5, R6, R7, R8, Ra, Rb, Rc, Rd, Re, and Rf are independently selected from hydrogen (H), substituted alkyl or unsubstituted alkyl; and X, Y, X?, and Y? are independently selected from nitrogen (N) and carbon (C).

Abstract: A coated chamber component comprises a chamber component and a coating deposited on a surface of the chamber component, the coating comprising an electrically-dissipative material. The electrically-dissipative material is to provide a dissipative path from the coating to a ground. The coating is uniform, conformal, and has a thickness ranging from about 10 nm to about 900 nm.

Abstract: Embodiments of the disclosure advantageously provide methods of manufacturing semiconductor devices having multi-Vt capability in the scaled space between nanosheets in advanced GAA nodes. One or more embodiments provide an integration scheme to advantageously reduce the gate resistance by combining n-/p-dipole and mid-gap metal with low resistance to achieve desired work function and low-resistance metal gate. In one or more embodiments, a mid-gap metal is used to fill nanosheets and act as a liner for subsequent fill by a low resistance metal. After dipole engineering, instead of filling the gate-all-around nanosheet with traditional n or p metal, in one or more embodiments, the nanosheet is advantageously filled with a single work function mid-gap metal to achieve n and p work function. If the work function was shifted in either P-dipole or N-dipole bandedge after dipole engineering, the mid-gap materials can also shift the bandedge the opposite way.

Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. Advantageously, the embodiments of the present disclosure provide methods of manufacturing electronic devices that achieve desired dipole effect without an annealing process. To achieve desired dipole effect that is “thinner” than 3 ?, embodiments of the disclosure advantageously include methods of controlling surface adsorption equilibrium and, in turn, controlling the fraction of substrate surface atomic sites that are occupied by dipole species, which is not considered to be achievable by ALD processes.

Abstract: Disclosed in some embodiments is a chamber component (such as an end effector body) coated with an ultrathin electrically-dissipative material to provide a dissipative path from the coating to the ground. The coating may be deposited via a chemical precursor deposition to provide a uniform, conformal, and porosity free coating in a cost effective manner. In an embodiment wherein the chamber component comprises an end effector body, the end effector body may further comprise replaceable contact pads for supporting a substrate and the contact surface of the contact pads head may also be coated with an electrically-dissipative material.

Abstract: Embodiments of the disclosure provide methods for fabricating or otherwise forming a protective coating containing cerium oxide on processing chamber surfaces and/or components, such as surfaces which are exposed to a plasma within a processing chamber. In one or more embodiments, a method of forming a protective coating within a processing chamber includes depositing a cerium oxide layer on a chamber surface or a chamber component during an atomic layer deposition (ALD) process. The ALD process includes sequentially exposing the chamber surface or the chamber component to a cerium precursor, a purge gas, an oxidizing agent, and the purge gas during an ALD cycle, and repeating the ALD cycle to deposit the cerium oxide layer.

Abstract: Implementations described herein generally relate to processes for the fabrication of semiconductor devices in which a blocking layer of molecules is used to achieve selective epitaxial deposition. In one implementation, a method of processing a mixed-surface substrate comprising an exposed dielectric material and an exposed silicon-based material is provided. The method comprises depositing a blocking layer on the exposed dielectric material and epitaxially and selectively depositing a silicon-containing material layer on the exposed silicon-based material at a temperature of 400 degrees Celsius or greater. The method further involves removing the blocking layer from the dielectric material.

Abstract: Exemplary semiconductor processing methods may include providing one or more deposition precursors to a semiconductor processing chamber. A substrate may be disposed within a processing region of the semiconductor processing chamber. The methods may include depositing a silicon-containing material on the substrate and on one or more components of the semiconductor processing chamber. The methods may include providing a fluorine-containing precursor to the processing region. The fluorine-containing precursor may be plasma-free when provided to the processing region. The methods may include contacting the silicon-containing material on the one or more components of the semiconductor processing chamber with the fluorine-containing precursor. The methods may include removing at least a portion of the silicon-containing material on the one or more components of the semiconductor processing chamber with the fluorine-containing precursor.

Abstract: A method of forming a high aspect ratio structure within a 3D NAND structure is provided. The method includes delivering a precursor to a high aspect ratio opening disposed within a multilayer stack having two or more alternating layers. The precursor is selected from the group consisting of a diaminosilane, an aminosilane, and a combination thereof. The method includes delivering an oxygen-containing compound to the high aspect ratio opening. The precursor and the oxygen-containing compound are alternated cyclically to fill the high aspect ratio opening.

Abstract: Embodiments of the disclosure provide a method of forming a dielectric film in trenches of a substrate. The utilization of the ALD process and introduction of an inhibitor material onto features defining the trenches and into the trenches provides for suppression of forming the dielectric film near the top surface of the features in the trenches. The dielectric film is formed via an ALD process. The ALD process includes sequentially exposing the substrate to an inhibitor material, a first precursor, a purge gas, an oxygen-containing precursor, and the purge gas during an ALD cycle, and repeating the ALD cycle to deposit the dielectric film.

Abstract: Exemplary methods of semiconductor processing may include providing a first precursor to a semiconductor processing chamber. A substrate may be disposed within a processing region of the semiconductor processing chamber. The first precursor may include a first metal. The methods may include contacting the substrate with the first precursor. The contacting may form a first portion of a metal oxide material on the substrate. The methods may include providing a second precursor to the semiconductor processing chamber. The second precursor may be an oxygen-containing precursor including an alcohol, an alkoxide, a hydroxide, an acetylacetonate, an acetate, a formate, a nitrate, a sulfate, a phosphate, a phosphide, a carbonate, an oxide, an oxynitride, a perchlorate, an oxyhalide, a peroxide, an oxalate, or a phenolate. The methods may include contacting the first portion of the metal oxide material with the second precursor. The contacting may form a metal oxide material.

Abstract: Exemplary methods of semiconductor processing may include providing a first precursor to a semiconductor processing chamber. A substrate may be disposed within a processing region of the semiconductor processing chamber. The first precursor may include one or more of niobium, tantalum, or titanium. The methods may include contacting the substrate with the first precursor. The contacting may form a layer of metal on the substrate. The methods may include providing a second precursor to a semiconductor processing chamber. The second precursor comprises oxygen. The methods may include contacting the layer of metal with the second precursor. The contacting may form a layer of metal oxide on the substrate. The layer of metal oxide may be one or more of niobium oxide, tantalum oxide, or titanium oxide.

Abstract: This disclosure pertains to coated drug compositions and methods of preparing coated drug compositions with a low temperature o-zone based silicon oxide coating. Specifically, the instant application discloses a method to coat active pharmaceutical ingredient particles using a silicon precursor and ozone at a low temperature.

Abstract: Methods of depositing a metal film by exposing a substrate surface to a halide precursor and an organosilane reactant are described. The halide precursor comprises a compound of general formula (I): MQzRm, wherein M is a metal, Q is a halogen selected from Cl, Br, F or I, z is from 1 to 6, R is selected from alkyl, CO, and cyclopentadienyl, and m is from 0 to 6. The aluminum reactant comprises a compound of general formula (II) or general formula (III): wherein R1, R2, R3, R4, R5, R6, R7, R8, Ra, Rb, Rc, Rd, Re, and Rf are independently selected from hydrogen (H), substituted alkyl or unsubstituted alkyl; and X, Y, X?, and Y? are independently selected from nitrogen (N) and carbon (C).

Abstract: Described herein are articles, systems and methods where a halogen resistant coating is deposited onto a surface of a chamber component using an atomic layer deposition (ALD) process. The halogen resistant coating has an optional amorphous seed layer and a transition metal-containing layer. The halogen resistant coating uniformly covers features of the chamber component, such as those having an aspect ratio of about 3:1 to about 300:1.