Patents by Inventor Geeyarpuram N. Santhanakrishnan
Geeyarpuram N. Santhanakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230088947Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.Type: ApplicationFiled: November 23, 2022Publication date: March 23, 2023Applicant: Intel CorporationInventors: Theodros Yigzaw, Geeyarpuram N. Santhanakrishnan, Ganapati N. Srinivasa, Jose A. Vargas, Hisham Shafi, Michael Mishaeli, Ehud Cohen, Zeev Sperber, Shlomo Raikin, Mohan J. Kumar, Julius Y. Mandelblat
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Publication number: 20210318932Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.Type: ApplicationFiled: June 23, 2021Publication date: October 14, 2021Applicant: Intel CorporationInventors: Theodros Yigzaw, Geeyarpuram N. Santhanakrishnan, Ganapati N. Srinivasa, Jose A. Vargas, Hisham Shafi, Michael Mishaeli, Ehud Cohen, Zeev Sperber, Shlomo Raikin, Mohan J. Kumar, Julius Y. Mandelblat
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Patent number: 11048587Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.Type: GrantFiled: March 4, 2019Date of Patent: June 29, 2021Assignee: Intel CorporationInventors: Theodros Yigzaw, Geeyarpuram N. Santhanakrishnan, Ganapati N. Srinivasa, Jose A. Vargas, Hisham Shafi, Michael Mishaeli, Ehud Cohen, Zeev Sperber, Shlomo Raikin, Mohan J. Kumar, Julius Y. Mandelblat
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Publication number: 20200004633Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.Type: ApplicationFiled: March 4, 2019Publication date: January 2, 2020Inventors: Theodros Yigzaw, Geeyarpuram N. Santhanakrishnan, Ganapati N. Srinivasa, Jose A. Vargas, Hisham Shafi, Michael Mishaeli, Ehud Cohen, Zeev Sperber, Shlomo Raikin, Mohan J. Kumar, Julius Y. Mandelblat
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Patent number: 10223204Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.Type: GrantFiled: December 22, 2011Date of Patent: March 5, 2019Assignee: Intel CorporationInventors: Theodros Yigzaw, Geeyarpuram N. Santhanakrishnan, Ganapati N. Srinivasa, Jose A. Vargas, Hisham Shafi, Michael Mishaeli, Ehud Cohen, Zeev Sperber, Shlomo Raikin, Mohan J. Kumar, Julius Y. Mandelblat
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Patent number: 9910807Abstract: Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed on a main board including multiple CPU sockets linked in communication via CPU socket-to-socket interconnect links forming a CPU socket-to-socket ring interconnect. The CPU's are also configured to transfer data between one another by sending data via the CPU socket-to-socket interconnects. Data may be transferred using a packetized protocol, such as QPI, and the CPU's may also be configured to support coherent memory transactions across CPU's.Type: GrantFiled: May 1, 2017Date of Patent: March 6, 2018Assignee: Intel CorporationInventors: Robert G. Blankenship, Geeyarpuram N. Santhanakrishnan, Yen-Cheng Liu, Bahaa Fahim, Ganapati N. Srinivasa
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Publication number: 20170235695Abstract: Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed on a main board including multiple CPU sockets linked in communication via CPU socket-to-socket interconnect links forming a CPU socket-to-socket ring interconnect. The CPU's are also configured to transfer data between one another by sending data via the CPU socket-to-socket interconnects. Data may be transferred using a packetized protocol, such as QPI, and the CPU's may also be configured to support coherent memory transactions across CPU's.Type: ApplicationFiled: May 1, 2017Publication date: August 17, 2017Applicant: lntel CorporationInventors: ROBERT G. BLANKENSHIP, GEEYARPURAM N. SANTHANAKRISHNAN, YEN-CHENG LIU, BAHAA FAHIM, GANAPATI N. SRINIVASA
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Patent number: 9639490Abstract: Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed on a main board including multiple CPU sockets linked in communication via CPU socket-to-socket interconnect links forming a CPU socket-to-socket ring interconnect. The CPU's are also configured to transfer data between one another by sending data via the CPU socket-to-socket interconnects. Data may be transferred using a packetized protocol, such as QPI, and the CPU's may also be configured to support coherent memory transactions across CPU's.Type: GrantFiled: November 29, 2011Date of Patent: May 2, 2017Assignee: Intel CorporationInventors: Robert G. Blankenship, Geeyarpuram N. Santhanakrishnan, Yen-Cheng Liu, Bahaa Fahim, Ganapati N. Srinivasa
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Patent number: 9575895Abstract: In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed.Type: GrantFiled: January 30, 2015Date of Patent: February 21, 2017Assignee: Intel CorporationInventors: Yen-Cheng Liu, Robert G. Blankenship, Geeyarpuram N. Santhanakrishnan, Ganapati N. Srinivasa, Kenneth C. Creta, Sridhar Muthrasanallur, Bahaa Fahim
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Patent number: 9448879Abstract: An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.Type: GrantFiled: December 22, 2011Date of Patent: September 20, 2016Assignee: INTEL CORPORATIONInventors: Theodros Yigzaw, Oded Lempel, Hisham Shafi, Geeyarpuram N. Santhanakrishnan, Jose A. Vargas, Ganapati N Srinivasa, Mohan J Kumar, Larisa Novakovsky, Lihu Rappoport, Chen Koren, Julius Mandelblat, Michael Mishaeli
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Publication number: 20150269104Abstract: Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed on a main board including multiple CPU sockets linked in communication via CPU socket-to-socket interconnect links forming a CPU socket-to-socket ring interconnect. The CPU's are also configured to transfer data between one another by sending data via the CPU socket-to-socket interconnects. Data may be transferred using a packetized protocol, such as QPI, and the CPU's may also be configured to support coherent memory transactions across CPU's.Type: ApplicationFiled: November 29, 2011Publication date: September 24, 2015Inventors: Robert G. Blankenship, Geeyarpuram N. Santhanakrishnan, Yen-Cheng Liu, Bahaa Fahim, Ganapati N. Srinivasa
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Publication number: 20150143051Abstract: In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed.Type: ApplicationFiled: January 30, 2015Publication date: May 21, 2015Inventors: Yen-Cheng Liu, Robert G. Blankenship, Geeyarpuram N. Santhanakrishnan, Ganapati N. Srinivasa, Kenneth C. Creta, Sridhar Muthrasanallur, Bahaa Fahim
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Patent number: 8984228Abstract: In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed.Type: GrantFiled: December 13, 2011Date of Patent: March 17, 2015Assignee: Intel CorporationInventors: Yen-Cheng Liu, Robert G. Blankenship, Geeyarpuram N. Santhanakrishnan, Ganapati N. Srinivasa, Kenneth C. Creta, Sridhar Muthrasanallur, Bahaa Fahim
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Publication number: 20130151782Abstract: In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed.Type: ApplicationFiled: December 13, 2011Publication date: June 13, 2013Inventors: Yen-Cheng Liu, Robert G. Blankenship, Geeyarpuram N. Santhanakrishnan, Ganapati N. Srinivasa, Kenneth C. Creta, Sridhar Muthrasanallur, Bahaa Fahim
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Patent number: 8347035Abstract: A processor may comprise a core area, a control unit, an uncore area. The core area may comprise multiple processing cores and line-fill buffers. A first processing core of the core area may store a first weakly ordered transaction in a first line-fill buffer. The firs processing core may offload the first weakly ordered transaction to the extended buffer space provisioned in the uncore area after receiving a request from the uncore area. The first processing core may then de-allocate the first line-fill buffer after the first weakly ordered transaction is offloaded to the extended buffer space. The uncore may then post the first weakly ordered transaction to a memory or a memory system. The control unit may track the first weakly ordered transaction to ensure that the first weakly ordered transaction is posted to the memory or the system.Type: GrantFiled: December 18, 2008Date of Patent: January 1, 2013Assignee: Intel CorporationInventors: Geeyarpuram N. Santhanakrishnan, Julius Mandelblat, Ehud Cohen, Larisa Novakovsky, Zeev Offen, Michelle J. Moravan, Shlomo Raikin, Ron Gabor
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Patent number: 8275942Abstract: According to one embodiment of the invention, a method is disclosed for selecting a first subset of a plurality of cache ways in a cache for storing hardware threads identified as high priority hardware threads for processing by a multi-threaded processor in communication with the cache; assigning high priority hardware threads to the selected first subset; monitoring a cache usage of a high priority hardware thread assigned to the selected first subset of plurality of cache ways; and reassigning the assigned high priority hardware thread to any cache way of the plurality of cache ways if the cache usage of the high priority hardware thread exceeds a predetermined inactive cache usage threshold value based on the monitoring.Type: GrantFiled: December 22, 2005Date of Patent: September 25, 2012Assignee: Intel CorporationInventors: Theodros Yigzaw, Geeyarpuram N. Santhanakrishnan, Mark Rowland, Ganapati Srinivasa
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Patent number: 8079031Abstract: A discussion of a dynamic configuration for a prefetcher is proposed. For example, a thread specific latency metric is calculated and provides dynamic feedback to the software on a per thread basis via the configuration and status registers. Likewise, the software can optionally use the information from the registers to dynamically configure the prefetching behavior and allows the software to be able to both query the performance and configure the prefetcher.Type: GrantFiled: October 21, 2005Date of Patent: December 13, 2011Assignee: Intel CorporationInventors: Geeyarpuram N. Santhanakrishnan, Michael F. Cole, Mark Rowland, Ganapati Srinivasa
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Patent number: 8074131Abstract: A high integration integrated circuit may comprise a plurality of processing cores, a graphics processing unit, and an uncore area coupled to an interface structure such as a ring structure. A generic debug external connection (GDXC) logic may be provisioned proximate to the end point of the ring structure. The GDXC logic may receive internal signals occurring in the uncore area, within the ring structure and on the interfaces provisioned between the plurality of cores and the ring structure. The GDXC logic may comprise a qualifier to selectively control the entry of the packets comprising information of the internal signals into the queue. The GDXC logic may then transfer the packets stored in the queues to a port provisioned on the surface of the integrated circuit packaging to provide an external interface to the analysis tools.Type: GrantFiled: June 30, 2009Date of Patent: December 6, 2011Assignee: Intel CorporationInventors: Tsvika Kurts, Guillermo Savransky, Jason Ratner, Eilon Hazan, Daniel Skaba, Sharon Elmosnino, Geeyarpuram N. Santhanakrishnan
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Publication number: 20100332927Abstract: A high integration integrated circuit may comprise a plurality of processing cores, a graphics processing unit, and an uncore area coupled to an interface structure such as a ring structure. A generic debug external connection (GDXC) logic may be provisioned proximate to the end point of the ring structure. The GDXC logic may receive internal signals occurring in the uncore area, within the ring structure and on the interfaces provisioned between the plurality of cores and the ring structure. The GDXC logic may comprise a qualifier to selectively control the entry of the packets comprising information of the internal signals into the queue. The GDXC logic may then transfer the packets stored in the queues to a port provisioned on the surface of the integrated circuit packaging to provide an external interface to the analysis tools.Type: ApplicationFiled: June 30, 2009Publication date: December 30, 2010Inventors: Tsvika Kurts, Guillermo Savransky, Jason Ratner, Eilon Hazan, Daniel Skaba, Sharon Elmosnino, Geeyarpuram N. Santhanakrishnan
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Publication number: 20100161907Abstract: A processor may comprise a core area, a control unit, an uncore area. The core area may comprise multiple processing cores and line-fill buffers. A first processing core of the core area may store a first weakly ordered transaction in a first line-fill buffer. The firs processing core may offload the first weakly ordered transaction to the extended buffer space provisioned in the uncore area after receiving a request from the uncore area. The first processing core may then de-allocate the first line-fill buffer after the first weakly ordered transaction is offloaded to the extended buffer space. The uncore may then post the first weakly ordered transaction to a memory or a memory system. The control unit may track the first weakly ordered transaction to ensure that the first weakly ordered transaction is posted to the memory or the system.Type: ApplicationFiled: December 18, 2008Publication date: June 24, 2010Inventors: Geeyarpuram N. Santhanakrishnan, Julius Mandelblat, Ehud Cohen, Larisa Novakovsky, Zeev Offen, Michelle J. Moravan, Shlomo Raikin, Ron Gabor