Abstract: The provided is flux-weakening control method and system for the salient pole offset permanent magnet synchronous motor. The method includes determining the given value of electromagnetic torque according to the actual speed and the given target speed; calculating the current trajectories of MTPA and MTPV in dq coordinate system; obtaining the d?q? coordinate system by rotating the coordinate system, and calculating the current trajectory of MTPA and MTPV in the d?q? coordinate system to obtain the characteristic current; judging whether it is necessary to turn on the flux-weakening control, and outputting the direct axis current compensation when it turns on; judging the flux-weakening area of the motor; and generating the space vector pulse width modulation signal to drive the motor to realize the full speed range flux-weakening speed regulation of the salient pole offset permanent magnet synchronous motor.

Abstract: The present disclosure provides a magnetic random-access memory cell, a memory and a device. The magnetic random-access memory cell comprises: a spin-orbit coupling layer and a first magnetic tunnel junction and a second magnetic tunnel junction disposed on the spin-orbit coupling layer, the first magnetic tunnel junction and the second magnetic tunnel junction having at least two symmetrical axes with different lengths; an angle between an easy magnetization symmetrical axis direction of a free layer of the first magnetic tunnel junction and a length direction of the spin-orbit coupling layer is a preset first angle, and an angle between an easy magnetization symmetrical axis direction of a free layer of the second magnetic tunnel junction and the length direction of the spin-orbit coupling layer is a preset second angle; neither of the first angle and the second angle is zero degree, 90 degrees or 180 degrees.

Abstract: Disclosed are a memory array, a memory, a preparing method and a writing method. Some embodiments relate to a memory array for a magnetoresistive random access memory and a manufacturing method thereof. The memory array includes: a plurality of memory cells arranged in an array and a conductor layer; each of the memory cells includes: a write transistor, a first end of which is coupled to top electrode wiring; a magnetic tunnel junction MTJ, one end of which close to a reference layer is coupled to a second end of the write transistor; a side surface of the conductor layer is coupled to end faces of one end of all of the magnetic tunnel junctions MTJs close to a free layer.

Abstract: The present disclosure provides a multi-bit memory cell, an analog-to-digital converter, a device and a method. The multi-bit memory cell comprises: a spin-orbit coupling layer and a plurality of magnetic tunnel junctions disposed on the spin-orbit coupling layer, the plurality of magnetic tunnel junctions comprising a plurality of first magnetic tunnel junctions; the plurality of first magnetic tunnel junctions are sequentially arranged along a length direction of the spin-orbit coupling layer, and critical currents of reversals of the magnetizations of free layers of the plurality of first magnetic tunnel junctions are progressively increased or decreased in sequence along the length direction. The present disclosure provides a multi-bit memory unit with simple manufacturing process and structure.

Abstract: The present disclosure provides a multi-bit memory cell, an analog-to-digital converter, a device and a method. The multi-bit memory cell comprises: a spin-orbit coupling layer and a plurality of magnetic tunnel junctions disposed on the spin-orbit coupling layer, the plurality of magnetic tunnel junctions comprising a plurality of first magnetic tunnel junctions; the plurality of first magnetic tunnel junctions are sequentially arranged along a length direction of the spin-orbit coupling layer, and critical currents of reversals of the magnetizations of free layers of the plurality of first magnetic tunnel junctions are progressively increased or decreased in sequence along the length direction. The present disclosure provides a multi-bit memory unit with simple manufacturing process and structure.

Abstract: The present disclosure provides a magnetic random-access memory cell, a memory and a device. The magnetic random-access memory cell comprises: a spin-orbit coupling layer and a first magnetic tunnel junction and a second magnetic tunnel junction disposed on the spin-orbit coupling layer, the first magnetic tunnel junction and the second magnetic tunnel junction having at least two symmetrical axes with different lengths; an angle between an easy magnetization symmetrical axis direction of a free layer of the first magnetic tunnel junction and a length direction of the spin-orbit coupling layer is a preset first angle, and an angle between an easy magnetization symmetrical axis direction of a free layer of the second magnetic tunnel junction and the length direction of the spin-orbit coupling layer is a preset second angle; neither of the first angle and the second angle is zero degree, 90 degrees or 180 degrees.

Abstract: A magnetic tunnel junction reference layer, magnetic tunnel junctions and a magnetic random access memory are provided, wherein the magnetic tunnel junction reference layer includes: an antiferromagnetic structure layer, which comprises a plurality of stacked metal magnetic layer units, wherein each of the metal magnetic layer units comprises a spacer layer and a magnetic layer on a surface of the spacer layer. The present invention forms a synthetic antiferromagnetic structure through multilayer stack of the metal spacer layer and the magnetic layer, so as to increase thermal stability of the magnetic tunnel junction reference layer with perpendicular magnetic anisotropy and reduce design complexity as well as cost of the film layers. The present invention forms a multilayer film structure without oxides, which has strong perpendicular magnetic anisotropy, high thermal stability, simple film layer, and low cost, thereby promoting large-scale use of the magnetic memory.