Abstract: A battery (400) comprising: an anode (300) and a cathode (401), and an electrolyte disposed between the anode and the cathode, wherein one or both of the anode and the cathode comprises an electrode comprising a plurality of sheets of graphene (101) and a plurality of carbon nanohorns (201) disposed between adjacent sheets and further comprises zinc (301). The plurality of carbon nanohorns may be arranged in a plurality of carbon nanohorn agglomerates (102).

Abstract: A method of forming a nanowire comprising: providing nanoparticles of a metallic material; providing a vapor of fluorocarbon molecules by heating a solid polymer; depositing at least some of the carbon of said molecules onto an exterior of one of said particles to form a deposit of carbon which surrounds at least part of the exterior of said one particle and assembling further of said particles with said one particle to form an elongate configuration of material in the form of a nanowire. Similar methods of production of nanotubes are also disclosed.

Abstract: A bipolar high voltage/power semiconductor device has a drift region having adjacent its ends regions of different conductivity types respectively. High and low voltage terminals are provided. A first insulated gate terminal and a second insulated gate terminal are also provided. One or more drive circuits provide appropriate voltages to the first and second insulated gate terminals so as to allow current conduction in a first direction or in a second direction that is opposite the first direction.

Abstract: A half bridge circuit has a first switch having at least one control gate and a second switch having at least two control gates. A first driver has an output connected to a control gate of the first switch. A second driver has an output connected to a first control gate of the second switch. The output of the first driver is connected to a second control gate of the second switch by a circuit arrangement such that when the first driver is operated to apply a high, positive voltage to the control gate of the first switch, a positive voltage is applied to the second control gate of the second switch, and such that when the first driver is operated to apply a low, zero or small voltage to the control gate of the first switch, a negative voltage is applied to said second control gate of the second switch.

Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

Abstract: A bipolar high voltage/power semiconductor device has a drift region having adjacent its ends regions of different conductivity types respectively. High and low voltage terminals are provided. A first insulated gate terminal and a second insulated gate terminal are also provided. One or more drive circuits provide appropriate voltages to the first and second insulated gate terminals so as to allow current conduction in a first direction or in a second direction that is opposite the first direction.

Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

Abstract: A semiconductor device having an active region is formed in a layer provided on a semiconductor substrate. At least a portion of the semiconductor substrate below at least a portion of the active region is removed such that the portion of the active region is provided in a membrane defined by that portion of the layer below which the semiconductor substrate has been removed. A heat conducting and electrically insulating layer is applied to the bottom surface of the membrane. The heat conducting and electrically insulating layer has a thermal conductivity that is higher than the thermal conductivity of the membrane so that the heat conducting and electrically insulating layer allows heat to pass from the active region into the heat conducting and electrically insulating layer during normal operation of the device.

Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

Abstract: A power semiconductor device (10) has an active region that includes a drift region (20). At least a portion of the drift region (20) is provided in a membrane (16) which has opposed top and bottom surfaces (15,17). In one embodiment, the top surface (15) of the membrane (16) has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region (20). In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface (15) and at least one electrical terminal is connected directly or indirectly to the bottom surface (17) to allow a voltage to be applied vertically across the drift region (20). In each of these embodiments, the bottom surface (17) of the membrane (16) does not have a semiconductor substrate positioned adjacent thereto.

Abstract: A semiconductor device having an active region is formed in a layer provided on a semiconductor substrate. At least a portion of the semiconductor substrate below at least a portion of the active region is removed such that the portion of the active region is provided in a membrane defined by that portion of the layer below which the semiconductor substrate has been removed. A heat conducting and electrically insulating layer is applied to the bottom surface of the membrane. The heat conducting and electrically insulating layer has a thermal conductivity that is higher than the thermal conductivity of the membrane so that the heat conducting and electrically insulating layer allows heat to pass from the active region into the heat conducting and electrically insulating layer during normal operation of the device.

Abstract: A semiconductor device having an active region is formed in a layer provided on a semiconductor substrate. At least a portion of the semiconductor substrate below at least a portion of the active region is removed such that the portion of the active region is provided in a membrane defined by that portion of the layer below which the semiconductor substrate has been removed. A heat conducting and electrically insulating layer is applied to the bottom surface of the membrane. The heat conducting and electrically insulating layer has a thermal conductivity that is higher than the thermal conductivity of the membrane so that the heat conducting and electrically insulating layer allows heat to pass from the active region into the heat conducting and electrically insulating layer during normal operation of the device.

Abstract: A semiconductor device (10) having an active region is formed in a layer (11) provided on a semiconductor substrate (13). At least a portion (13′) of the semiconductor substrate (13) below at least a portion of the active region is removed such that the portion of the active region is provided in a membrane (14) defined by that portion of the layer (11) below which the semiconductor substrate (13) has been removed. A heat conducting and electrically insulating layer (20) is applied to the bottom surface (16) of the membrane (14). The heat conducting and electrically insulating layer (20) has a thermal conductivity that is higher than the thermal conductivity of the membrane (14) so that the heat conducting and electrically insulating layer (20) allows heat to pass from the active region into the heat conducting and electrically insulating layer (20) during normal operation of the device (10).

Abstract: A MOS-controllable power semiconductor trench device has a gate in the form of a trench which extends through a region of p type silicon into an n type region of low conductivity. A discontinous buried p layer below the bottom of the trench forms part of a thyristor which in operation is triggered into conduction by conduction of a PIN diode which is produced when an accumulation layer is formed in the n type region adjacent to the trench under the action of an on-state gate signal. The device has a high on-state conductivity and is protected against high voltage breakdown in its off-state by the presence of the buried layer. An off-state gate signal causes removal of the accumulation layer and conduction of the PIN diode and the thyristor ceases in safe, reliable and rapid manner.

Abstract: An Insulated Gate Bipolar Transistor has a gate in the form of a trench positioned in a p region in a silicon body. The device operates in a thyristor mode having a virtual emitter which is formed during operation by the generation of an inversion layer at the bottom of the trench within the p region. The device is inherently safe and turns off rapidly as removal of a gate signal collapses the emitter. As the trench gate is situated within the p region, it can withstand high voltages when turned off as the reverse electric field is prevented from reaching the trench gate.