Patents by Inventor Gehan Amaratunga

Gehan Amaratunga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100178531
    Abstract: An energy storage device structure comprises a first electrode layer, an electrolyte layer and a second electrode layer. At least one of the electrode layers comprise a metallic base layer, a layer of carbon nanotubes grown on the base layer and a layer of carbon nanoparticles disposed on the carbon nanotube layer, the carbon nanoparticle layer being arranged to face the electrolyte layer. The structure has much larger width and length than thickness, so it is rolled up or folded and then hermetically sealed to form an energy storage unit. The layer of carbon nanotubes is grown on the metallic base layer by a chemical vapor deposition process at a temperature no higher than 550° C. The carbon nanotubes in the carbon nanotube layer are at least partially aligned in a direction that is perpendicular to the surface of the metallic base layer.
    Type: Application
    Filed: January 13, 2009
    Publication date: July 15, 2010
    Inventors: Gehan Amaratunga, Haolan Wang, Husnu Emrah Unalan, Markku Antti Kyosti Rouvala, Di Wei
  • Patent number: 7551460
    Abstract: This invention relates to switch mode power supply (SMPS) controllers employing primary side sensing. We describe an (SMPS) controller which uses an area correlator to compare an area under a feedback signal waveform between a start point defined by said first timing signal and an end point defined by said second timing signal with a reference area. An output of the area correlator provides an error signal for regulating the SMPS output.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: June 23, 2009
    Assignee: Cambridge Semiconductor Limited
    Inventors: Vinod A. Lalithambika, Devarahandi Indika Mahaesh de Silva, Jayaraman Kumar, Gehan Amaratunga
  • Publication number: 20080055952
    Abstract: A DC to AC power converter is disclosed. The power converter comprises four power-switching devices, two diodes, a step-up and isolation transformer, a capacitor-choke filter and a controller. Two power-switching devices located on the primary side of the transformer are switched to provide alternate cycles of an ac current to the primary side of the transformer, which magnetically couples the ac current to the secondary side of the transformer. Two power-switching devices on the secondary side of the transformer are switched to alternately allow the forward and return ac currents from the secondary side of the transformer in the output path to a load connected to the output of the DC to AC power converter.
    Type: Application
    Filed: June 29, 2007
    Publication date: March 6, 2008
    Inventors: Lesley Chisenga, Asim Mumtaz, Gehan Amaratunga
  • Publication number: 20070274112
    Abstract: This invention relates to switch mode power supply (SMPS) controllers employing primary side sensing. We describe an (SMPS) controller which uses an area correlator to compare an area under a feedback signal waveform between a start point defined by said first timing signal and an end point defined by said second timing signal with a reference area. An output of the area correlator provides an error signal for regulating the SMPS output.
    Type: Application
    Filed: June 1, 2006
    Publication date: November 29, 2007
    Inventors: Vinod A. Lalithambika, Devarahandi Indika Mahesh de Silva, Jayaraman Kumar, Gehan Amaratunga
  • Publication number: 20060067137
    Abstract: A high voltage/power semiconductor device has at least one active region having a plurality of high voltage junctions electrically connected in parallel. At least part of each of the high voltage junctions is located in or on a respective membrane such that the active region is provided at least in part over plural membranes. There are non-membrane regions between the membranes. The device has a low voltage terminal and a high voltage terminal. At least a portion of the low voltage terminal and at least a portion of the high voltage terminal are connected directly or indirectly to a respective one of the high voltage junctions. At least those portions of the high voltage terminal that are in direct or indirect contact with one of the high voltage junctions are located on or in a respective one of the plural membranes.
    Type: Application
    Filed: September 1, 2005
    Publication date: March 30, 2006
    Applicant: CAMBRIDGE SEMICONDUCTOR LIMITED
    Inventors: Florin Udrea, Gehan Amaratunga
  • Publication number: 20060049406
    Abstract: This invention is generally concerned with power semiconductors such as power MOS transistors, insulated gate by bipolar transistors (IGBTs), high voltage diodes and the like, and methods for their fabrication. A power semiconductor, the semiconductor comprising: a power device, said power device having first and second electrical contact regions and a drift region extending therebetween; and a semiconductor substrate mounting said device; and wherein said power semiconductor includes an electrically insulating layer between said semiconductor substrate and said power device, said electrically insulating layer having a thickness of at least 5 ?m.
    Type: Application
    Filed: September 9, 2004
    Publication date: March 9, 2006
    Inventors: Gehan Amaratunga, Florin Udrea
  • Publication number: 20050242368
    Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.
    Type: Application
    Filed: July 6, 2005
    Publication date: November 3, 2005
    Applicant: CAMBRIDGE SEMICONDUCTOR LIMITED
    Inventors: Florin Udrea, Gehan Amaratunga
  • Publication number: 20050242369
    Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.
    Type: Application
    Filed: July 6, 2005
    Publication date: November 3, 2005
    Applicant: CAMBRIDGE SEMICONDUCTOR LIMITED
    Inventors: Florin Udrea, Gehan Amaratunga
  • Publication number: 20050172370
    Abstract: A method of forming a nanowire comprising: providing nanoparticles of a metallic material; providing a vapour of fluorocarbon molecules by heating a solid polymer; depositing at least some of the carbon of said molecules onto an exterior of one of said particles to form a deposit of carbon which surrounds at least part of the exterior of said one particle and assembling further of said particles with said one particle to form an elongate configuration of material in the form of a nanowire. Similar methods of production of nanotubes are also disclosed.
    Type: Application
    Filed: November 4, 2004
    Publication date: August 4, 2005
    Inventors: Sajad Haq, Ioannis Alexandrou, Gehan Amaratunga, Khai Ang
  • Publication number: 20050121309
    Abstract: A method of providing nanoparticles, especially carbon nanoonions, comprises generating an arc discharge between an anode and a cathode, both being submerged in a liquid and collecting the nanoparticles from the surface of the liquid, which may be an aqueous liquid, liquid ammonia, liquid helium, ethanol, methanol. Acetone, toluene, or chloroform.
    Type: Application
    Filed: September 11, 2002
    Publication date: June 9, 2005
    Inventors: Manish Chhowalla, Gehan Amaratunga, Noriaki Sano, Haolan Wang
  • Publication number: 20020041003
    Abstract: A power semiconductor device (10) has an active region that includes a drift region (20). At least a portion of the drift region (20) is provided in a membrane (16) which has opposed top and bottom surfaces (15, 17). In one embodiment, the top surface (15) of the membrane (16) has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region (20). In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface (15) and at least one electrical terminal is connected directly or indirectly to the bottom surface (17) to allow a voltage to be applied vertically across the drift region (20). In each of these embodiments, the bottom surface (17) of the membrane (16) does not have a semiconductor substrate positioned adjacent thereto.
    Type: Application
    Filed: September 21, 2001
    Publication date: April 11, 2002
    Applicant: CAMBRIDGE SEMICONDUCTOR LIMITED
    Inventors: Florin Udrea, Gehan Amaratunga
  • Patent number: 5489787
    Abstract: An insulated gate field effect device (1a,1b,1c,1d) has a semiconductor body (2) with a first region (3) of one conductivity type, a second region (4) of the opposite conductivity type, a third region (6) of the one conductivity type (7) separated from the first region (3) by the second region (4) and at least one injector region (8) for injecting charge carriers of the opposite conductivity type into the first region (3). The conduction channel area (40) adjoining the insulated gate (9, 10) has first and second subsidiary areas (40 and 40b) for providing respective first and second subsidiary conduction channels.
    Type: Grant
    Filed: July 6, 1994
    Date of Patent: February 6, 1996
    Assignee: U.S. Philips Corporation
    Inventors: Gehan A. Amaratunga, Florin Udrea