Abstract: A data bus system utilizing logical transfer channels provides high data rates (even over long distances) and good error detection. The basic function of a transfer channel is to enable temporary assignment of some portion of the bus resource to a specific device and then to allow simple, quick addressing of that device by reference to that channel. There are a relatively small number of transfer channels (say four) that may be attached or detached by the channel processor (IOCP) to meet the data flow requirements. For a transfer to occur between the IOCP (15) and a device (30a, 30b), the IOCP (15) first effects an "attach" operation to assign the device (30a, 30b) a transfer channel for the duration of the transfer. Thereafter, the IOCP (15) allocates the bus cycles among the currently attached transfer channels according to any desired priority scheme, subject to the constraint that the device on a transfer channel be ready to send or receive data before that transfer channel may be granted cycles.

Abstract: Fully synchronous operation is provided by the use of separate frame and clock signals in each of the two directions relative to the IOCP, with all these signals controlled by the IOCP. The transmit (outbound) clock and frame signals (TCLK and TFRM) are simply sent on two lines from the IOCP to a bus terminator at the far end with the devices connecting to these lines in sequence. The receive (inbound) clock and frame signals (RCLK and RFRM) also originate at the IOCP, but their lines go directly to the far end where they are turned around and sent back to the IOCP with the devices being coupled to these lines in the reverse sequence. This provides a pair of signals that travel toward the IOCP but are still controlled by it for timing the incoming data.