Patents by Inventor Geir MYRVÅGNES

Geir MYRVÅGNES has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • A METHOD OF CONTROLLED N-DOPING OF GROUP III-V MATERIALS GROWN ON (111) SI
    Publication number: 20220259758
    Abstract: The present invention is related to a method of providing n-doped group III-V materials grown on (111) Si, and especially to a method comprising steps of growth of group III-V materials interleaved with steps of no growth, wherein both growth steps and no growth steps are subject to a constant uninterrupted arsenic flux concentration.
    Type: Application
    Filed: July 7, 2020
    Publication date: August 18, 2022
    Applicant: Integrated Solar
    Inventors: Renato BUGGE, Geir MYRVÅGNES
  • METHOD OF EPITAXIAL GROWTH OF A MATERIAL INTERFACE BETWEEN GROUP III-V MATERIALS AND SILICON WAFERS PROVIDING COUNTERBALANCING OF RESIDUAL STRAINS
    Publication number: 20190252571
    Abstract: The present invention relates to a method of manufacturing semiconductor materials comprising interface layers of group III-V materials in combination with Si substrates. Especially the present invention is related to a method of manufacturing semiconductor materials comprising GaAs in combination with Si(111) substrates, wherein residual strain due to different thermal expansion coefficient of respective materials is counteracted by introducing added layer(s) compensating the residual strain.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Inventors: Renato BUGGE, Geir MYRVÅGNES
  • A METHOD OF EPITAXIAL GROWTH OF A MATERIAL INTERFACE BETWEEN GROUP III-V MATERIALS AND SILICON WAFERS PROVIDING COUNTERBALANCING OF RESIDUAL STRAINS
    Publication number: 20170352536
    Abstract: The present invention relates to a method of manufacturing semiconductor materials comprising interface layers of group III-V materials in combination with Si substrates. Especially the present invention is related to a method of manufacturing semiconductor materials comprising GaAs in combination with Si(111) substrates, wherein residual strain due to different thermal expansion coefficient of respective materials is counteracted by introducing added layer(s) compensating the residual strain.
    Type: Application
    Filed: December 23, 2015
    Publication date: December 7, 2017
    Inventors: Renato BUGGE, Geir MYRVÅGNES