Abstract: Methods for extreme ultraviolet (EUV) mask defect mitigation by using multi-patterning lithography techniques. In one exemplary embodiment, a method for fabricating an integrated circuit including identifying a position of a defect in a first EUV photolithographic mask, the photolithographic mask including a desired pattern and transferring the desired pattern to a photoresist material disposed on a semiconductor substrate. Transferring the desired pattern further transfers an error pattern feature to the photoresist material as a result of the defect in the first EUV photolithographic mask. The method further includes, using a second photolithographic mask, transferring a trim pattern to the photoresist material, wherein the trim pattern removes the error pattern feature from the photoresist material.

Abstract: A pellicle is provided for use with a lithographic photomask during manufacture of semiconductor devices, printed circuit boards, liquid crystal displays, etc. The pellicle has a pellicle frame comprising four pellicle walls that define a trapezoidal area sized and shaped to correspond to a pattern area of a lithographic photomask; and a pellicle film extending across the trapezoidal area and affixed to a film-side edge of the pellicle frame; wherein any one of the four pellicle walls has a vent hole therethrough, the vent hole being located proximate a corner of the frame and if matter passes through the vent hole, the foreign matter will not obstruct the pattern area during use of the lithographic photomask.

Abstract: Methods for extreme ultraviolet (EUV) mask defect mitigation by using multi-patterning lithography techniques. In one exemplary embodiment, a method for fabricating an integrated circuit including identifying a position of a defect in a first EUV photolithographic mask, the photolithographic mask including a desired pattern and transferring the desired pattern to a photoresist material disposed on a semiconductor substrate. Transferring the desired pattern further transfers an error pattern feature to the photoresist material as a result of the defect in the first EUV photolithographic mask. The method further includes, using a second photolithographic mask, transferring a trim pattern to the photoresist material, wherein the trim pattern removes the error pattern feature from the photoresist material.

Abstract: A pellicle is provided for use with a lithographic photomask during manufacture of semiconductor devices, printed circuit boards, liquid crystal displays, etc. The pellicle has a pellicle frame comprising four pellicle walls that define a trapezoidal area sized and shaped to correspond to a pattern area of a lithographic photomask; and a pellicle film extending across the trapezoidal area and affixed to a film-side edge of the pellicle frame; wherein any one of the four pellicle walls has a vent hole therethrough, the vent hole being located proximate a corner of the frame and if matter passes through the vent hole, the foreign matter will not obstruct the pattern area during use of the lithographic photomask.

Abstract: System and methods for OPC model accuracy and disposition using quad matrix are presented. A method includes obtaining wafer data from a calibration test pattern. The method also classifies the wafer data into four quadrants of a quad matrix. The method further utilizes at least one of the four quadrants to quantify OPC model accuracy.

Abstract: Methods for extreme ultraviolet (EUV) mask defect mitigation by using multi-patterning lithography techniques. In one exemplary embodiment, a method for fabricating an integrated circuit including identifying a position of a defect in a first EUV photolithographic mask, the photolithographic mask including a desired pattern and transferring the desired pattern to a photoresist material disposed on a semiconductor substrate. Transferring the desired pattern further transfers an error pattern feature to the photoresist material as a result of the defect in the first EUV photolithographic mask. The method further includes, using a second photolithographic mask, transferring a trim pattern to the photoresist material, wherein the trim pattern removes the error pattern feature from the photoresist material.

Abstract: Methods for extreme ultraviolet (EUV) mask defect mitigation by using multi-patterning lithography techniques. In one exemplary embodiment, a method for fabricating an integrated circuit including identifying a position of a defect in a first EUV photolithographic mask, the photolithographic mask including a desired pattern and transferring the desired pattern to a photoresist material disposed on a semiconductor substrate. Transferring the desired pattern further transfers an error pattern feature to the photoresist material as a result of the defect in the first EUV photolithographic mask. The method further includes, using a second photolithographic mask, transferring a trim pattern to the photoresist material, wherein the trim pattern removes the error pattern feature from the photoresist material.

Abstract: System and methods for OPC model accuracy and disposition using quad matrix are presented. A method includes obtaining wafer data from a calibration test pattern. The method also classifies the wafer data into four quadrants of a quad matrix. The method further utilizes at least one of the four quadrants to quantify OPC model accuracy.

Abstract: An approach is provided for enabling simulation of photomask contour shapes, performing verification on the simulated photomask shapes, and correcting errors in OPC correction or bad fracturing methods to perform photomask proximity correction in real time before physically writing of the photomask. Embodiments include performing optical proximity correction of a photomask of a semiconductor layout to generate a corrected photomask, simulating the corrected photomask to generate one or more simulated contour shapes within a simulated photomask, verifying the simulated contour shapes to determine errors associated with the simulated photomask, and correcting the errors in the simulated contour shapes of the simulated photomask to generate a final photomask.

Abstract: System and methods for OPC model accuracy and disposition using quad matrix are presented. A method includes obtaining wafer data from a calibration test pattern. The method also classifies the wafer data into four quadrants of a quad matrix. The method further utilizes at least one of the four quadrants to quantify OPC model accuracy.

Abstract: System and methods for OPC model accuracy and disposition using quad matrix are presented. A method includes obtaining wafer data from a calibration test pattern. The method also classifies the wafer data into four quadrants of a quad matrix. The method further utilizes at least one of the four quadrants to quantify OPC model accuracy.

Abstract: An approach for methodology, and an associated apparatus, enabling a simulation process to check integrity of the design and predict a manufacturability of a resulting circuit that accounts for process latitude without a long turnaround time and/or a highly skilled engineer is disclosed. Embodiments include: determining first and second features of an IC design; determining a thickness of a resist layer of the IC design based on an aerial image of the IC design; determining a threshold value according to the thickness; and comparing the threshold value to a separation distance between the first and second features.

Abstract: An approach for methodology, and an associated apparatus, enabling a simulation process to check integrity of the design and predict a manufacturability of a resulting circuit that accounts for process latitude without a long turnaround time and/or a highly skilled engineer is disclosed. Embodiments include: determining first and second features of an IC design; determining a thickness of a resist layer of the IC design based on an aerial image of the IC design; determining a threshold value according to the thickness; and comparing the threshold value to a separation distance between the first and second features.

Abstract: An approach is provided for enabling simulation of photomask contour shapes, performing verification on the simulated photomask shapes, and correcting errors in OPC correction or bad fracturing methods to perform photomask proximity correction in real time before physically writing of the photomask. Embodiments include performing optical proximity correction of a photomask of a semiconductor layout to generate a corrected photomask, simulating the corrected photomask to generate one or more simulated contour shapes within a simulated photomask, verifying the simulated contour shapes to determine errors associated with the simulated photomask, and correcting the errors in the simulated contour shapes of the simulated photomask to generate a final photomask.

Abstract: A method for fabricating a semiconductor device that includes: providing a substrate prepared with a photoresist layer; providing a photomask comprising a first and a second pattern having a respective first and second pitch range; providing a composite aperture comprising a first and a second off-axis illumination aperture pattern, the first off-axis aperture pattern having a configuration that improves the process window of the first pitch range and the second off-axis aperture pattern having a configuration that improves the process window for a second pitch range; exposing the photoresist layer on the substrate with radiation from an exposure source through the composite aperture and the photomask; and developing the photoresist layer to pattern the photoresist layer.

Abstract: A method of manufacture of a mask system includes: providing design data; generating a substantially circular optical proximity correction target from the design data; biasing a segment of the substantially circular optical proximity correction target; and generating mask data based on the shape produced by biasing the segment of the substantially circular optical proximity correction target.

Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate having a photoresist thereon and transmitting a light source through a mask having a pattern onto the photoresist. The mask comprises a mask substrate having first, second and third regions, the third region is disposed between the first and second regions. The mask also includes a light reducing layer over the mask substrate having a first opening over the first region and a second opening over the second region. The first and second openings have layer sidewalls. The sidewalls of the light reducing layer are slanted at an angle less than 90 degrees from the plane of a top surface of the mask substrate. The method also includes developing the photoresist to transfer the pattern of the mask to the photoresist.

Abstract: A method of fabricating a device is presented. The method includes forming a mask that includes multiple images. A substrate is patterned using the mask. An image of the multiple images corresponds to a respective patterning process. The substrate is processed further to complete the processing of the substrate to form the desired function of the device.

Abstract: Apparatus is provided for determining presence of contamination on a lithography mask, including: a fluid trap having a base and at least one wall member extending substantially perpendicularly to the base for trapping fluid on a portion of the base when fluid introduced during a cleaning process of the mask is removed.

Abstract: A reticle system that includes: providing a reticle system; and assigning two or more of an image pattern onto the reticle system to form one or more layers of an integrated circuit system by grouping and pairing each of the image pattern onto the reticle system according to a multi-layer reticle grouping/pairing flow.